Semiconductor integrated circuit device
AssigneesNippon Telegraph & Telephone Public Corporation, Fujitsu Limited
InventorsKuniyasu Kawarada, Masao Suzuki, Chikai Ono, Kazuhiro Toyoda
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Abstract
A semiconductor integrated circuit device has an array of memory cells formed by integrated injection logic. A desired number of dummy cells are provided at both ends of each line of the array, so that a write current, which flows when the memory cell near the dummy cell is selected, is shunted by the dummy cell, thereby the currents which flow in the memory cells in the line of the memory array are equalized.
Claims19
A semiconductor integrated circuit device having an array of integrated injection logic memory cells, each said cell comprising first and second transistors of first conduction type with emitters connected in common to form an injector of said cell, third and fourth transistors of a second conduction type opposite said first type having their collectors respectively connected to the collectors of said first and second transistors, said third transistor having its base is connected to said collector of said fourth transistor and said fourth transistor having its base connected to said collector of said third transistor, and said first and second transistors having their bases connected in common with the emitters of said third and fourth transistors;
- said device comprising
- a first word line connecting said injectors of said cell,
- a second word line comprising a bulk portion of said semiconductor of said device selectively connected to said commonly connected bases of said first and second transistors and said emitters of said third and fourth transistors, and
- at least one dummy cell at each end of each said of said array, each said dummy cell comprising means for shunting a respective portion of a write current which flows when one of said integrated injection logic memory cells near said dummy cell is selected.
A semiconductor integrated circuit device having an array of integrated injection logic memory cells, formed with semiconductor material, said cells being selectively connected to respective first and second word lines and first and second bit lines to define lines of said cells in said array, each said integrated injection logic memory cell comprised of first and second transistors having emitters of a first conduction type with a common emitter forming an injector of the cell, a pair of third and fourth transistors having emitters of a second conduction type opposite said first type and having collectors respectively connected to the collectors of said first and second transistors, said injector being connected to the respective first word line, said third transistor having its base connected to the collector of said fourth transistor and said fourth transistor having its base connected to the collector of said third transistor, said first and second transistors having their bases connected in common to the emitters of said third and fourth transistors and to the respective second word line, and means for providing a write current selectively to said cells, said semiconductor integrated circuit device further comprising
- means for equalizing said injection current to each of said cells, near the ends of said lines of said array, said means comprising
- a bulk portion of said semiconductor material comprising each said second word line, and
- at least one dummy cell at the end of each said line of said memory cell array, each said dummy cell comprising means for shunting a respective portion of said write current corresponding to any of said integrated injection logic memory cells that are selected near dummy cell.
The device of claim 18 comprising a single dummy cell at each end of each line of said array, each said diode comprising an injector area that is larger than the corresponding area of said memory cell injector.
Dependencies are inferred from the claim text.