Three phase line-addressable serial-parallel-serial storage array

A controlled three phase line-addressable serial-parallel-serial storage array comprising:

• a serial input register for accepting data bits at an input;
• a serial output register for providing data bits at an output;
• a parallel register having a plurality of parallel columns, each said column arranged between a storage position in said input register and a storage position in said output register, for receiving data bits from said serial input register and for transferring data bits to said serial output register;
• first, second, and third phase lines connected to each said registers;
• and
• control lines connected to each said registers, each one of said control lines being adapted to selectively inhibit the propagation of data bits in said registers;
• the first, second, and third phase lines connected to the parallel register being arranged in parallel to each other, and orthogonally to said columns, each said first, second and third phase lines being associated with one row of said parallel register;
• the control lines connected to the parallel register being arranged in parallel to each other, and orthogonally to said first, second, and third phase lines, each said control lines extending along one of the columns of the parallel register such that a control signal applied by means of one or more of said control lines to a desired one or more of the columns selectively inhibits or permits data bit propagation from one row of said parallel register to another along said one or more columns.