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US 4,194,132 AGranted
Tristate logic buffer circuit with reduced power consumption
AssigneeNational Semiconductor Corporation
InventorDale A. Mrazek
Life of this patent
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Abstract
A current mirror transistor is included in a tristate logic buffer circuit, with its base and emitter respectively connected to the base and emitter of the phase splitter transistor and its collector connected to the voltage supply terminal. A high resistance connected between the voltage supply terminal and the collector of the phase splitter transistor causes the circuit to consume less power when the circuit is disabled; and the current mirror transistor supplements the drive current provided by the phase splitter transistor when the circuit is not disabled.
Claims6
A tristate logic buffer circuit, comprising
- a data input terminal;
- a multi-emitter input transistor, having a first emitter connected to the data input terminal for receiving a digital data input signal;
- a voltage supply terminal
- a first resistance for coupling the base of the input transistor to the voltage supply terminal;
- a phase splitter transistor having its base coupled to the collector of the input transistor;
- a second resistance for coupling the collector of the phase splitter transistor to the voltage supply terminal;
- a data output terminal;
- a pull-down transistor having its base coupled to the emitter of the phase splitter transistor, its emitter coupled to a circuit ground terminal, and its collector connected to the data output terminal;
- a third resistance coupled between the base and emitter of the pull-down output transistor;
- a pull-up output transistor having its emitter connected to the data output terminal, its collector coupled to the voltage supply terminal, and its base coupled to the collector of the phase splitter transistor;
- a circuit disable terminal connected to a second emitter of the input transistor;
- and
- a diode having its anode connected to the collector of the phase splitter transistor and its cathode connected to the circuit disable terminal;
- wherein, when a "high" logic signal is applied at the circuit disable terminal, a digital data output signal that is the logical complement of the digital data input signal is provided at the data output terminal;
- and when a "low" logic signal is applied at the circuit disable terminal the circuit has a high output impedance between the data output terminal and circuit ground to inhibit the provision of said digital data output signal;
- wherein the improvement comprises
- a current mirror transistor having its base and emitter respectively connected to the base and emitter of the phase splitter transistor and its collector connected to the voltage supply terminal.
14 more elements
Dependencies are inferred from the claim text.