Master-slave flip-flop circuit
AssigneeNippon Electric Co., Ltd.
InventorsToru Takahashi, Kodo Kimura
Life of this patent
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Abstract
A logic circuit, which includes master-slave flip-flops, advantageously designed to place both the master and the slave flip-flops in a predetermined logic state so that the logic circuit can be tested in one clock cycle in the same manner as a combinational logic circuit is tested.
Claims6
A logic circuit comprising a plurality of master-slave flip-flops, said master-slave flip-flops including master flip-flops and slave flip-flops having mutually complementary clock signals applied thereto,
- means for selectively producing a test signal, and
- means responsive to the test signal for placing, at the same time, the master flip-flops and slave flip-flops in an enable condition.
A logic circuit comprising a master flip-flop and a slave flip-flop, first means responsive to a first state of a clock signal for placing the master flip-flop in a first logic state, second means responsive to a second state of the clock signal, complementary to said first state, for placing the slave flip-flop in a second logic state, and third means responsive to the application of a test signal to the logic circuit for simultaneously placing the master flip-flop and the slave flip-flop in the first logic state irrespective of the state of the clock signal.
A logic circuit comprising a master flip-flop including first and second nodes, first and second common nodes, a first transistor having a collector coupled to said first node, a base coupled to said second node and an emitter coupled to said first common node, a second transistor having a collector coupled to said second node, a base coupled to said first node and an emitter coupled to said first common node, a third transistor having a collector coupled to said first node, a base supplied with input information and an emitter coupled to said second common node, a fourth transistor having a collector coupled to said second node, a base supplied with a reference voltage and an emitter coupled to said second common node, first current source means, a fifth transistor having a collector coupled to said second common node and an emitter coupled to said first current source means, and a sixth transistor having a collector coupled to said first common node, a base supplied with a reference voltage and an emitter coupled to said first current source means, a slave flip-flop including third and fourth nodes, third and fourth common nodes, a seventh transistor having a collector coupled to said third node, a base coupled to said fourth node, and an emitter coupled to said third common node, a eighth transistor having a collector coupled to said fourth node, a base coupled to said third node, and an emitter coupled to said third common node, a ninth transistor having a collector coupled to said third node, a base supplied with a signal derived from said second node and an emitter coupled to said fourth common node, a tenth transistor having a collector coupled to said fourth node, a base supplied with a reference voltage and an emitter coupled to said fourth common node, second current source means, an eleventh transistor having a collector coupled to said fourth common node and an emitter coupled to said second current source means, and a twelfth transistor having a collector coupled to said third common node, a base supplied with a reference voltage and an emitter coupled to said second current source means, first means responsive to a first state of a clock signal for turning on said fifth transistor, second means responsive to a second state of the clock signal complementary to said first state for turning on said eleventh transistor and third means responsive to a test signal for turning on said fifth and eleventh transistors irrespective of said clock signal.
Dependencies are inferred from the claim text.