High density N-channel silicon gate read only memory
AssigneeTexas Instruments Incorporated
InventorDavid J. McElroy
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AssigneeTexas Instruments Incorporated
InventorDavid J. McElroy
Estimating the term…
An N-channel silicon gate read only memory or ROM array of very high bit density is made by providing columns in the form of parallel N+ moats separated by field oxide and removing small areas of the field oxide in a pattern of "1's" and "0's" according to the ROM program. Gate oxide is grown in the areas where field oxide is removed, and parallel polycrystalline silicon strips are laid down over the field oxide and gate oxide areas normal to the moats, providing the rows. The ROM may be made as part of a standard double level poly, N-channel, self-aligned silicon gate process. The columns may include an output line and several intermediate lines for each ground line so that a virtual ground format is provided. An implant step may be used to avoid the effects of exposed gate oxide so that zero-overlap design rules are permitted.
A method of making a semiconductor device comprising the steps of masking a plurality of parallel elongated regions of a face of a semiconductor body against oxidation, growing thick field oxide in the spaces between the elongated regions but not above the elongated regions, removing small areas of the field oxide in a pattern according to where functioning transistors are to be created, forming thin gate dielectric in said small areas, and applying a plurality of parallel elongated conductive strips over the field oxide and gate dielectric in a direction normal to the elongated regions.
A method of making a semiconductor device comprising the steps of:
A method of making an N-channel read only memory comprising the steps of:
Dependencies are inferred from the claim text.