Display controller for time recorders and time actuators
AssigneeOsborne-Hoffman, Inc.
InventorPaul W. Osborne
Life of this patent
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Abstract
A display controller interacts with a plurality of time recorders and time actuators such that the display controller displays the time recorded in a plurality of time recorders, and controls the predetermined sequence of output states in a plurality of time actuators. Time recorders and time actuators of small size and low power consumption result from the use of this invention.
Claims5
A device for recording the time of occurrence of an event and transmitting said time of occurrence over a single output line in binary serial format, one bit a time, comprising:
- (a) an input line over which a triggering signal is applied upon occurrence of an event,
- (b) a digital clock emitting clock pulses,
- (c) a counter generating shifting pulses and a trigger pulse each frame driven by clock pulses from said digital clock,
- (d) a shift register whose contents are shifted by shifting pulses from said counter, the length of the shift register being equal to one frame,
- (e) a pulse generator triggered by said counter generating a pulse each frame until halted by an external triggering signal upon occurrence of an event,
- (f) an adder driven by said pulse generator and said shift register and recirculating its output to said shift register thereby augmenting the count of pulses in said shift register until the occurrence of an event, and maintaining the count thereafter,
- (g) a single output line over which the content of said shift register is transmitted in binary serial format one bit at a time.
A time actuator providing level shifting signal means over a time actuation line at preprogrammed times, said preprogramming being provided over a single time load line, comprising:
- (a) said time load line providing means of presetting the count in a shift register,
- (b) a digital clock emitting clock pulses,
- (c) a counter generating shifting pulses and a trigger pulse each frame driven by clock pulses from said digital clock,
- (d) said shift register preset by serial pulses from the time load line, whose contents are shifted by shifting pulses from said counter, the length of the shift register being equal to one frame,
- (e) a pulse generator triggered by said counter generating a pulse each frame,
- (f) an adder driven by said pulse generator and said shift register and recirculating its output to said shift register thereby augmenting the count of pulses in said shift register until the shift register has been filled following which cycle time actuation is reached,
- (g) a second adder driven by said shift register and said first adder resulting in a reset pulse at the output of the second adder, and
- (h) a flip-flop having its state reset by a reset pulse from said second adder when time actuation is reached.
Dependencies are inferred from the claim text.