Arithmetic synthesizer frequency generation with reduced phase jitter
AssigneeRCA Corporation
InventorsEdward J. Nossen, Eugene R. Starner
Life of this patent
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Abstract
Arithmetic synthesizer having an output circuit that provides a linear phase output signal. A ramp generator controlled by the stepped output signal from the arithmetic synthesizer interpolates the value of the signal slope between steps to supply a phase output having low noise, i.e., reduced time jitter.
Claims5
In an arithmetic synthesizer including means for supplying digital signals representing a frequency number, means for supplying clock signals, accumulator means for periodically accumulating said digital signals representing a frequency number to produce digital sum signals having a given modulus, and digital-to-analog conversion means receptive of said digital sum signals for producing analog signals representative of said digital sum signals, the improvement comprising:
- output means responsive to said analog signals for producing output signals representing the instantaneous value of the average slope of said digital signals;
- said output means including means for mixing said output signals and said digital signals to produce difference signals;
- and
- said output means further including sweep generator means responsive to said difference signals for producing said output signals having a linear slope determined by the value of said difference signals.
Dependencies are inferred from the claim text.