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US 4,132,904 AGranted
Volatile/non-volatile logic latch circuit
AssigneeHughes Aircraft Company
InventorEliyahou Harari
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AssigneeHughes Aircraft Company
InventorEliyahou Harari
Estimating the term…
There is described a logic element employing fixed threshold and variable threshold transistors electrically connected together in a unique manner to form a latch. The latch can be made to retain data by keeping certain internal nodes at a high or low voltage level. As such it acts as an ordinary semiconductor memory latch, whose data can be changed by externally overriding the internal voltage levels of the latch cell. The novel results of the cell described are achieved by replacing one or several of the transistors in the latch by specially constructed transistors, whose threshold voltage can be raised or lowered upon application of a relatively high voltage pulse between their gate and substrate. By application of such a high voltage pulse, the data stored in the latch can be translated into controlled threshold shifts of the variable threshold transistors, which uniquely represent the initial latch state. Therefore, if power is removed and then returned, the latch will always settle into a state dictated by the final state that existed in the latch before the high voltage pulse was applied. In this way the variable threshold elements of the latch cell make it a non-volatile memory element. It can be used either as a read/write memory, using its latch property, or as a read-only memory, using the variable threshold transistors to cause it to always latch in a predetermined manner.
A bistable latch circuit having a pair of branches connected across a common supply voltage, each branch including a load and a driver connected in series at a respective node, either the load or the driver, or both, in each said branch comprising an IGFET having its source-to-drain circuit connected in said branch and its control gate cross-connected to the node of the other branch so that, when a respective one of said IGFETs is turned on, the potential between said nodes rises toward said supply voltage, the relative potentials of said nodes reflecting the particular IFGET so turned on, thereby rendering said circuit bistable for volatile information storage, characterized by at least one of said cross-connected IGFETs having a variable threshold voltage, said threshold voltage being varied by raising its gate potential above a predetermined level relative to the potential on one of its other electrodes, whereby the volatile information stored in said latch by placing it in one of its stable states may be rendered non-volatile by raising said supply voltage above said predetermined level.
An integrated semiconductor memory latch circuit comprising in combination:
An integrated semiconductor memory latch circuit comprising in combination:
An integrated semiconductor memory latch circuit comprising in combination:
An integrated semiconductor memory latch circuit comprising in combination:
An integrated semiconductor memory latch circuit comprising in combination:
An integrated semiconductor memory latch circuit comprising in combination:
An integrated semiconductor memory latch circuit comprising in combination a pair of branches, each branch including an IGFET load and an IGFET driver connected in series, drain-to-drain at a node, the control gate of the IGFET driver of each branch being connected to the node of the other branch, one and only one of said IGFET drivers having a floating gate with a thin oxide area at least partially over the node to which said one IGFET driver is connected and extending from said IGFET driver to the channel area of the IGFET load in its branch, said IGFET driver and the IGFET load in its branch interconnected control gates, with the control gate of said IGFET driver being capacitively coupled to the floating gate of said driver.
Dependencies are inferred from the claim text.