Two-phase CCD regenerator - I/O circuits

A charge coupled device memory including a first charge coupled device shift register structure having an output region and a second charge coupled device shift register structure having an input region, phased clock pulse means coupled to said shift register structures for shifting charge in said shift register structures;

• and charge regenerator means coupled between said output region and said input region, said charge regenerator means comprising a source follower insulated gate field effect transistor amplifier means including a driver transistor, a load transistor and a positive feedback transistor connected between the gate and source of said driver transistor, an output transistor gate connected between said output region and the gate of said driver transistor for sensing a binary data charge level at said output region and to bias said driver transistor to a conductive state in response to a sensed charge level corresponding to one binary level and to a non-conductive state in response to a sensed charge level corresponding to the other binary level;
• means connecting the output of said source follower amplifier means to said input region to insert a first predetermined charge corresponding to said one binary data level in response to said output transistor gate sensing a charge level corresponding to said one binary data level and a second predetermined charge corresponding to the other binary data level in response to said output transistor gate sensing a charge level corresponding to that other binary data level;
• and further transistor gating means for precharging the gate of said driver transistor to a predetermined level prior to sensing of said output region charge level by said output transistor gate.

A charge coupled device memory including at least first and second charge coupled device shift register structures each having an output region and an input region, phased clock pulse means coupled to said shift register structures for shifting charge in said shift register structures;

• first and second charge regenerator means cross coupling said output regions with said input regions, each of said charge regenerator means comprising:
• a source follower insulated gate field effect transistor amplifier means including a driver transistor, a load transistor and a positive feedback transistor connected between the gate and source of said driver transistor, an output transistor gate connected between the output region of one of said shift register structures and the gate of said driver transistor for sensing a binary data charge level at said output region and to bias said driver transistor to a conductive state in response to a sensed charge level corresponding to one binary level and to a non-conductive state in response to a sensed charge level corresponding to the other binary level;
• means connecting the output of said source follower amplifier means to the input region of the other said shift register structure to insert a first predetermined charge corresponding to said one binary data level in response to said output transistor gate sensing a charge level corresponding to said one binary data level and to insert a second predetermined charge corresponding to the other binary data level in response to said output transistor gate sensing a charge level corresponding to that other binary data level;
• and further transistor gating means for precharging the gate of said driver transistor to a predetermined level prior to sensing of said output region charge level by said output transistor gate;
• and further including semiconductor gating means for selectively and non-destructively sensing charge level at the output of one of said source follower amplifier means to generate a corresponding binary level output signal, and for selectively entering a predetermined charge corresponding to one or the other of said binary data levels into the input region to which that said source follower amplifier means is connected.