US 4,085,288 A · Phase locked loop decoder

Abstract

A phase locked loop decoder for decoding digitally encoded data is disclosed in which each incoming data bit is synchronized to a clock frequency and a derived signal representative of the data cell width is varied in accordance with a derived phase error signal to compensate for bit shift and for data cell width variation which may be present in the incoming data. The phase error signal is a pulsed waveform having a leading edge synchronized with the occurrence of each data transition and a pulse width reprsentative of the phase error of the data with respect to the clock. The decoder will detect and decode data transitions having bit shifts of up to plus or minus 50 percent of the bit cell period.

Claims16

Dependent claims

Phase locked loop decoder for decoding data signals having a given frequency and representative of digitally encoded data bits, each bit being encoded within a bit cell, comprising:

clock means for generating a data clocking signal for each bit cell;
phase error detection means for generating a digital pulsed phase error signal having a leading edge synchronized with the occurrence of each transition of said data signal within each bit cell and having a pulse width representative of the difference in time of occurrence of said data signal with respect to said cell clocking signal, and having an output;
clock synchronizing means responsive to said phase error signal for maintaining substantially continuous synchronization between said data signals and said clocking signal by advancing or retarding subsequent clocking signals;
and
data decoder means synchronized by said clocking signal for decoding said output of said phase error detection means at said given frequency.

2 more elements

A system for decoding data encoded on a magnetic medium comprising:

means for deriving a digital data input signal representative of said encoded data, said data input signal having a varying frequency and varying data bit cell widths;
phase locked loop means for generating a clock signal at a varying frequency such that said clock signal is substantially continuously synchronized with said data input signal, and having an output;
decoding means for decoding the output of said phase locked loop means at a frequency determined by said clock signal, and
phase error signal generation means associated with said phase locked loop means for generating a digital pulsed phase error signal having a leading edge synchronized with the occurrence of each transition of said data input signal and having a pulse width representative of the difference in time of occurrence of said data signal with respect to said clock signal, for advancing or retarding said clock signal to drive said substantially continuously synchronized clock signal.

1 more element

Dependencies are inferred from the claim text.

Phase locked loop decoder

Life of this patent

Phase locked loop decoder

Life of this patent

Abstract

Claims16