Integrated FET circuit with input current cancellation

A leakage compensated FET integrated circuit assembly, comprising:

• an integrated circuit chip having a P-type substrate and an N-type epitaxial region,
• a primary FET on said chip comprising a source, a drain, a channel, and a gate, said source and drain comprising mutually spaced means formed on a portion of said epitaxial region and connected by said channel, and said gate comprising said epitaxial portion,
• an isolation pocket for said FET having a boundary region which comprises the portion of the substrate adjacent said epitaxial portion together with isolation means extending into said epitaxial region to isolate the FET portion thereof, said substrate and isolation means being of opposite conductivity type material from said epitaxial region and drawing a gate leakage current therefrom when said epitaxial region is reverse biased with respect to said substrate and isolation means,
• a leakage analog to said FET comprising a second isolation pocket, a multicollector lateral PNP transistor in said pocket employing the epitaxial region of said second pocket for a base, a first one of its collectors being connected to its base to establish a reference leakage current to said pocket the magnitude of which is a substantially fixed proportion of the gate leakage current from said FET to said first pocket over a given operating range, and a second one of its collectors forming a proportional current mirror tracking said reference current and connected to the FET epitaxial region to supply a current thereto which is substantially equal to the FET gate leakage current, thereby substantially cancelling the FET input current that would otherwise be required to supply said leakage current, and
• voltage shifting means coupling the gate of said FET with the emitter of said transistor to maintain the base voltage level close to but greater than that of the gate by an amount sufficient to keep the junction between the second collector and the base of said transistor reverse biased.

In an integrated circuit operational amplifier, a leakage compensated input stage comprising:

• an integrated circuit chip having a substrate adapted to be connected to a negative supply voltage, and an epitaxial region formed on the substrate,
• input stage circuit means including first and second substantially identical primary FET's, each of said FET's comprising a source, a drain, a channel, and a gate, the source and drain for each FET comprising mutually spaced means formed on said epitaxial region and connected by said channel, and the gate for each FET comprising the portion of the epitaxial region adjacent said channel,
• an isolation pocket for each of said FET's, each of said pockets having a boundary region which comprises isolation means extending into the epitaxial region to laterally isolate its respective FET, and the portion of the substrate adjacent the FET, said substrate and isolation means being of opposite conductivity type material from said epitaxial region and drawing gate leakage currents from the FET portions thereof when said portions are reverse biased with respect to said substrate and isolation means,
• amplifier input terminals associated with each of said FET gates,
• a leakage analog associated with each FET, each analog comprising means on said chip for establishing a reference current the magnitude of which is a substantially fixed proportion of the gate leakage current of its associated FET, and proportional current mirror means tracking said reference current to provide a current which is substantially equal to the gate leakage current of its associated FET,
• each of said proportional current mirror means being connected to the epitaxial region of its associated FET to supply the gate leakage current thereof and thereby substantially cancel the input current that would otherwise be required to supply said leakage current.