Junction field effect transistor of vertical type

Abstract

A junction field effect transistor of a vertical type having: a drain region having a first conductivity type; a gate region composed of branches formed on said drain region by a selective vapor deposition or liquidous phase deposition method and having a second conductivity type opposite to the first conductivity type of the drain region, at least that surface of each of the branches of the gate region which locates on the side opposite to the drain region side being covered with an insulating layer; and source regions formed between the respective branches of the gate region by conducting a further growth of said drain region. This field effect transistor has a sufficiently reduced area of P - N junction between the gate region and the respective source regions, resulting in a marked reduction in the junction capacitance. Besides, the insulated gate region with respect to the source regions give rise to a high gate-to-source breakdown voltage property.

Dependencies are inferred from the claim text.