MNOS Memory device
AssigneeMcDonnell Douglas Corporation
InventorYukun Hsia
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Abstract
A method for fabricating a variable threshold IGFET free of parasitic effects and the "floating gate" effect. The IGFET includes an oxide layer having a portion of minimum thickness in the region thereof overlying an interstitial portion of a semiconductive substrate having a pair of spaced semiconductive diffusion regions, a portion of intermediate thickness partially overlying at least one of the pair of diffusion regions and the interstitial substrate portion, and a remaining portion of maximum thickness. The oxide layer portion of minimum thickness has a width greater than the width of an overlying electrically conductive gate electrode; the oxide layer portion of intermediate thickness has a width less than the width of the overlying electrode.
Claims16
An insulative gate field effect transistor comprising:
- a semiconductive substrate of a first conductivity type;
- a pair of spaced semiconductive diffusion regions of opposite conductivity type to said substrate formed in said substrate, said diffusion regions being separated by an interstitial portion of said substrate and sharing a common boundary surface therewith;
- a layer of oxide material adhered to said common boundary surface, said layer having a portion of minimum thickness in the region thereof overlying said interstitial portion of said substrate, a portion of intermediate thickness partially overlying at least one of said pair of diffusion regions and said interstitial portion of said substrate, and a remaining portion of maximum thickness;
- a layer of dielectric material adhered to said oxide layer;
- and
- an electrically conductive electrode of predetermined width adhered to said dielectric layer in the region overlying said interstitial substrate portion;
- said oxide layer portion of minimum thickness having a width greater than the width of said electrically conductive electrode to define with the overlying portion of said dielectric layer and the underlying portion of said semiconductive substrate an insulative gate region;
- said oxide layer portion of intermediate thickness having a width less than the width of said electrically conductive electrode to define with the underlying portion of said semiconductive substrate an MOS gate region.
Dependencies are inferred from the claim text.