Circuit arrangement for the protection of inputs of integrated MOS circuits
AssigneeSiemens Aktiengesellschaft
InventorHeinrich Hubert Kessler
Life of this patent
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Abstract
A circuit arrangement for the protection of inputs of integrated MOS circuits against excessive voltages, for example as a consequence of static charges, includes a first circuit means connected to the MOS circuit and having two bypass circuits reacting at different input voltage values and having a high-ohmic compensating resistance, and second circuit means is connected ahead of the first circuit and comprises a bypass circuit and a high-ohmic compensating resistance.
Claims2
A protection circuit for protecting an input of an integrated MOS circuit against excessive voltages, the integrated MOS circuit connected across first and second supply terminals, comprising:
- an input;
- a pn bypass diode connected between said input and the first supply terminal;
- a first MOS transistor including a source-drain path connected between the second supply terminal and an input of said MOS circuit and a gate connected to said input of said MOS circuit;
- a gate controlled pn diode connected between said input of said MOS circuit and the first supply terminal;
- a first resistor connected with a first terminal to said input of said MOS circuit;
- a second MOS transistor including a source-drain path connected between a second terminal of said first resistor and said first supply terminal and a gate connected to said second terminal of said first resistor;
- and
- a second resistor connected between said second terminal of said first resistor and said input.
Dependencies are inferred from the claim text.