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AssigneeTexas Instruments Incorporated
InventorsAl F. Tasch, Jr, Robert Charles Frye, Horng-Sen Fu, Robert W. Brodersen
Estimating the term…
Semiconductor memory cells include gate conductor-insulator-semiconductor regions having storage and transfer portions in which the threshold voltage and surface potential-gate conductor voltage characteristics differ as between the storage and transfer portions. This may be achieved by employing relatively thick and relatively thin insulator areas at the storage and transfer portions, or vice versa, with a surface charge accumulation layer at the semiconductor region insulator interface. In a different form of cell structure, the insulator is a uniform thickness layer overlying the storage and transfer portions one of which includes a doped semiconductor region of the same conductivity type as, but higher dopant concentration than, the remainder of the semiconductor region. The difference in threshold voltage and surface potential characteristics is such that in response to first and second defined gate voltage levels, the potential well profile at the storage and transfer portions is changed in a manner permitting write in and read out of logic signal level related charge packets into and from the storage portion. Semiconductor memories include a matrix array of such cell structures, the gate conductor of a line of cells in the matrix forming part of a store/word conductor common to that line and a sense portion of each cell may form part of a common sense line for a line of cells extending perpendicularly to the store/word conductors. The memory cells may be fabricated by a process utilizing photolithographic alignment offset and self-aligning techniques in conjunction with diffusion and ion implantation techniques.
A memory cell for a semiconductor memory device, comprising a gate conductor-insulator-semiconductor region, the semiconductor of said region having one conductivity type and including a storage portion and an adjacent transfer portion with at least part of the gate conductor of said region overlying and electrically coupled to both said storage and transfer portions for receiving clock pulses to create potential wells at said storage and transfer portions, the semiconductor of said region further including a sense portion adjacent said transfer portion for receiving signal charge corresponding to logic 1 and logic 0 signal levels for writing into and read-out from said storage portion, and for receiving signal charge corresponding to logic 1 and logic 0 signal levels read-out from said storage portion, the conductor-insulator-semiconductor region at said storage and transfer portions having differing threshold voltage and semiconductor surface potential-gate voltage characteristics such that responsive to a selected first clock pulse level applied to said gate conductor, potential wells of different depths are created at said storage and transfer portions with the potential well at said storage portion being deeper than that at said transfer portion for writing logic signal charge inputs from said sense portion into said storage portion, and responsive to a second selected clock pulse level potential wells having a lesser difference in depth are created at said storage and transfer portions with the potential well at said transfer portion being deeper than that at said storage portion for reading logic signal charge from said storage portion into said sense portion.
A semiconductor memory comprising a semiconductor substrate having an insulating layer on one surface thereof, said memory including a matrix of cells, each said cell comprising a gate conductor-insulator-semiconductor region, the semiconductor of said region having one conductivity type and including a storage portion adjacent to a transfer portion, said gate conductor comprising a portion of a store/word conductor electrically coupled to and overlying both the storage and transfer portions of a line of said cells, and a portion of said semiconductor of each cell region adjacent said transfer portion defining a sense portion for receiving logic 1 and logic 0 signal charge levels for writing into said storage portion of said cell and for receiving logic 1 and logic 0 signal charge levels read-out from said storage portion under control of clock pulses applied to said store/word conductors, said conductor insulator-semiconductor region of each cell having gate conductor voltage-surface potential and threshold voltage characteristics differing as between said transfer and storage portions of that cell such that in response to a first clock pulse voltage level, differential depth potential wells are created at said transfer and storage portions with the potential well created at the storage portion being deeper than that at the transfer portion to permit entry of logic signal charge inputs into the storage portion of a cell from the sense portion of said cell, and responsive to a selected second clock pulse voltage potential wells having smaller differential depths are created at said transfer and storage portions of that cell with the potential well created at the transfer portion being deeper than that at the storage portion for read-out of binary logic signal charge from the storage portion of that cell to the sense portion thereof.
Dependencies are inferred from the claim text.