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US 4,059,826 AGranted
Semiconductor memory array with field effect transistors programmable by alteration of threshold voltage
AssigneeTexas Instruments Incorporated
InventorGerald D. Rogers
Life of this patent
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Abstract
N-channel silicon gate MOS memory cells are programmed by an ion implant step which is done prior to forming the gates or the diffused source and drain regions. The implanted devices have a threshold voltage which is about zero, so the devices cannot be turned off at usual logic levels. Either ROM or RAM arrays can be made using implant for programming.
Claims9
A semiconductor memory comprising:
- a. an array of rows and columns of memory cells on a face of a semiconductor body;
- b. an MOS transistor included in each of said memory cells, each MOS transistor having gate, source and drain regions and a channel region, insulator material above the channel region and beneath the gate being much thinner than surrounding insulator material on said face;
- c. selected ones of the channel regions of the MOS transistors being implanted with conductivity-detemining imputities to a depth much less than that of the source and drain regions and to an extent whereby the threshold voltage is substantially zero and the source and drain regions are essentially shorted together at zero volts on the gate, to thereby permanently program certain cells of the memory.
A method of programming a semiconductor memory comprising the steps of:
- a. providing a body of semiconductor material having an array of locations on a major face thereof which are the channel areas of MOS transistors;
- b. masking said one face with a meterial substantially impervious to an ion beam, apertures being defined in the material at selected ones of said locations where a selected logic level is to be permanently programmed;
- c. exposing said face to a beam of conductivity determining impurity atoms of an energy level and for a time sufficient to create an implanted region at each aperture to change the threshold voltage of the resulting MOS transistor to a voltage level of substantially zero;
- d. and thereafter forming a gate above each channel region separated therefrom by a thin gate oxide and forming source and drain regions for the MOS transistors and interconnections to provide an array of cells the source and drain regions being diffused to a depth much greater than the implanted regions.
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Dependencies are inferred from the claim text.