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US 4,056,810 AGranted
Integrated injection logic memory circuit
AssigneeU.S. Phillips Corporation
InventorsCornelis Maria Hart, Arie Slob
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AssigneeU.S. Phillips Corporation
InventorsCornelis Maria Hart, Arie Slob
Estimating the term…
A new integrated circuit in which bias currents are supplied by means of a current injector, a multi-layer structure in which current is supplied, by means of injection and collection of charge carriers via rectifying junctions, to zones to be biased of circuit elements of the circuit, preferably in the form of charge carriers which are collected by the zones to be biased themselves from one of the layers of the current injector. By means of said current injector circuit arrangements can be realized without load resistors being necessary, while the wiring pattern may be very simple and the packing density of the circuit elements may be very high. In addition a simple method of manufacturing with comparatively few operations can in many cases be used in particular upon application of transistors having a structure which is inverted relative to the conventional structure.
An integrated semiconductor memory comprising a plurality of groups of first, second, and third transistors each having emitter, base and collector, first and second transistors in each group being connected to form a plurality of cross-coupled trigger flip-flop circuits, said plurality of trigger circuits being arranged in rows and columns, the third transistors being complementary to the first and second transistors, a first read-write line commonly coupled to a column of trigger circuits, means connecting the first read-write line through the emitter-collector path of the third transistor to the base of the first transistor in that group, means for providing a circuit path from the emitters of the first and second transistors to a point of reference potential, a current injector coupled to the base zones of the first and second transistors and capable when forward biased of injecting carriers from a region outside of the first and second transistors and causing collection of the same or corresponding carriers by said base zones biasing the first and second transistors into operative condition, and a voltage supply line connected to the current injector.
An integrated semiconductor memory comprising a plurality of groups of first, second, third and fourth transistors each having emitter, base and collector, first and second transistors in each group being connected to form a plurality of cross-coupled trigger flip-flop circuits, said plurality of trigger circuits being arranged in rows and columns, means connecting the collector of the third and fourth transistors in each group to the bases respectively of the first and second transistors in the same group, first and second write lines commonly coupled to a column of trigger circuits, means for connecting the emitters of the first, second, third and fourth transistors to a point of reference potential, first and second current injectors each comprising means responsive to a forward bias for injecting carriers which when collected by a transistor zone will bias said zone into operation, a voltage supply line connected to the first current injector, means for coupling the first current injector to the base zones of the first and second transistors of all of the trigger circuits, a selection line connected to the second current injector, and means for coupling the second current injector to the base zones of the third and fourth transistors of a row of trigger circuits.
Dependencies are inferred from the claim text.