I.I.L. with region connecting base of double diffused injector to substrate/emitter of switching transistor

An integrated injection logic semiconductor device, which comprises a one conductivity type semiconductor substrate;

• an opposite conductivity type semiconductor layer superposed on said semiconductor substrate and having a lower impurity concentration than the semiconductor substrate;
• a first one conductivity type region formed in said opposite conductivity type semiconductor layer;
• opposite conductivity type region formed in said first one conductivity type region;
• at least one second region of one conductivity type formed in said opposite conductivity type semiconductor layer;
• an insulation separating region surrounding said first and second one conductivity type regions penetrating said opposite conductivity type semiconductor layer to contact said one conductivity type semiconductor substrate;
• and a connector region of one conductivity type formed in said opposite conductivity type semiconductor layer disposed beneath and more heavily doped than said first one conductivity type region for connection between said first one conductivity type region and said one conductivity type semiconductor substrate through a part of said first one conductivity type region, wherein said opposite conductivity type region, said first one conductivity type region, and said opposite conductivity type semiconductor layer jointly constitute a lateral transistor and said one conductivity type substrate, said opposite conductivity type semiconductor layer and said second one conductivity type region collectively form a vertical transistor.

An integrated injection logic semiconductor device, which comprises an N type semiconductor substrate;

• a P type semiconductor layer superposed on said N type semiconductor substrate and having a lower impurity concentration than the semiconductor substrate;
• a first N type region formed in said P type semiconductor layer;
• a P type region formed in said first N type region;
• at least one second N type region formed in said P type semiconductor layer;
• and an N.sup.+ type connector region formed in said P type semiconductor layer disposed beneath said first N type region for connection between said first N type region and said N type semiconductor substrate through a part of said first N type region, wherein said P type region, said first N type region, and said P type semiconductor layer jointly constitute a lateral transistor and said N type substrate, said P type semiconductor layer and said second N type region collectively form a vertical transistor.