Isolated semiconductor gate control circuit

Abstract

A circuit for the generation or development of a gating signal for a semiconductor device which is isolated from the circuit of the device itself is comprised of a pulse generating section which feeds pulses to the primary winding of a transformer to thereby induce pulses into the transformer secondary winding. An output section is connected to the secondary winding of the transformer which provides alternately, relatively positive and negative going output signals which serve as the gating signals for the semiconductor device. As provided in the preferred embodiment, the semiconductor device is a field effect transistor and the output section insures that during times in which it is desired to have the transistor conducting, a relatively positive pulse is applied to the gate electrode of the field effect transistor while during periods between pulses, when it is desired to have the transistor non-conducting, there is a sufficiently negative signal applied to the gate electrode so as to maintain the field effect transistor in its nonconducting state.

Dependencies are inferred from the claim text.