US 4,051,389 AGranted

Flip-flop circuit

AssigneeHitachi, Ltd.

InventorsKenji Kaneko, Takahiro Okabe

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Abstract

A flip-flop circuit comprises a pair of inversely operated first and second npn vertical transistors. The first npn transistor has dual collectors. Also provided are a pair of first and second pnp lateral transistors operated as loads and a pair of third and fourth pnp lateral transistors for triggering, each base of the first and second npn vertical transistors being connected to a collector of the second npn transistor and to one of the dual collectors of the first npn transistor, respectively. Each collector of the first and second pnp transistors is connected to said one of the dual collectors of the first npn transistor and to the collector of the second npn transistor, respectively. Each emitter of the first and second pnp transistors is connected to an electric source, each base of the first and second npn transistors is connected to each emitter of the third and fourth pnp transistors, respectively, and each base of the third and fourth pnp transistors is connected to said one of the dual collectors of the first npn transistor through a first resistor and to the collector of the second npn transistor through a second resistor. Each collector of the third and fourth pnp transistors is connected to an input terminal for trigger signals, an output terminal is connected to the other collector of the dual collectors of the first npn transistor, and each emitter of the first and second npn transistors and each base of said first and second pnp transistors is grounded.

Claims7

Dependent claims

A trigger-type flip-flop circuit comprising:

a pair of inversely operated vertical type first and second transistors, said first transistor having dual collectors;
a pair of lateral type third and fourth transistors, each having a polarity opposite to that of said first transistor and operated as a load;
a pair of triggering fifth and sixth transistors, each of which has a polarity opposite to that of said first transistor;
the bases of said first and second transistors being connected to the collector of said second transistor and to one of the dual collectors of said first transistor, respectively;
the collectors of said third and fourth transistors being connected to said one of the dual collectors of said first transistor and to the collector of said second transistor, respectively;
the emitters of said third and fourth transistors being connected to a first power supply means;
the bases of said first and second transistors being connected to the emitters of said fifth and sixth transistors, respectively;
the bases of said fifth and sixth transistors being connected to said one of the dual collectors of said first transistor through first delay means and to the collector of said second transistor through second delay means, respectively;
the collectors of said fifth and sixth transistors being connected to an input terminal for trigger signals;
an output terminal connected to the other collector of the dual collectors of said first transistor;
the emitters of said first and second transistors being electrically connected to a ground terminal;
and
the bases of said third and fourth transistors being electrically connected to said ground terminal.

10 more elements

Dependencies are inferred from the claim text.