Memory circuit

A memory circuit comprising:

• a semiconductor element circuit having equivalently a PNPN four-layer structure including a P-type emitter, an N-type base, a P-type base and an N-type emitter;
• first, second and third resistors;
• at least an NPN transistor;
• and
• a diode;
• wherein said N-type emitter of said semiconductor element circuit is connected to the base of said NPN transistor and said P-type base of said semiconductor element circuit is connected to the anode of said diode, the cathode of said diode being connected to the collector of said NPN transistor, said collector being used for a current absorbing terminal, one terminal of said first resistor is connected to said N-type base of said semiconductor element circuit, the other terminal of said first resistor being used for another current absorbing terminal, the second resistor is connected between said P-type base and said N-type emitter of said semiconductor element circuit, and the third resistor is connected between the base and the emitter of said NPN transistor.

A memory circuit comprising:

• a semiconductor element circuit having equivalently a PNPN four-layer structure including a P-type emitter, an N-type base, a P-type base and an N-type emitter;
• first, second, third and fourth resistors;
• at least an NPN transistor;
• and
• a diode;
• wherein said N-type emitter of said semiconductor element circuit is connected to the base of said NPN transistor, said P-type base of said semiconductor element circuit is connected to the anode of said diode, the cathode of said diode being coupled to the collector of said NPN transistor through the fourth resistor, one terminal of said first resistor is connected to said N-type base of said semiconductor element circuit, the other terminal of the first resistor being used for a current absorbing terminal, the second resistor is connected between said P-type base and said N-type emitter of said semiconductor element circuit, and the third resistor is connected between the base and the emitter of said NPN transistor.

A memory circuit comprising:

• a semiconductor element circuit having equivalently a PNPN four-layer structure including a P-type emitter used as an anode, an N-type base, a P-type base and an N-type emitter used as a cathode;
• first, second and third resistors;
• first, second and third diodes;
• and
• at least an NPN transistor, wherein
• said N-type emitter of said semiconductor element circuit is connected to the anode of said first diode, the cathode of said first diode being connected to the base of said NPN transistor, the cathode of said second diode is connected to the anode of said third diode, and said P-type base of said semiconductor element circuit is connected to the anode of said second diode, and cathode of said third diode is connected to the collector of said NPN transistor, one terminal of the first resistor is connected to said N-type base of said semiconductor element circuit and the other terminal of said first resistor being used for a current absorbing terminal, the second resistor is connected between said P-type base and said N-type emitter of said semiconductor element circuit, and the third resistor is connected between the base and the emitter of said NPN transistor.

A memory circuit comprising:

• a semiconductor element circuit having equivalently a PNPN four-layer structure including a P-type emitter, an N-type base, a P-type base and an N-type emitter and inherently having a positive feedback loop circuit;
• another feedback loop circuit in cooperation with the positive feedback loop circuit including an NPN transistor and at least one diode having its anode connected with said P-type base of said semiconductor element circuit and its cathode connected with the collector of said NPN transistor;
• and
• means for setting said NPN transistor in a controlled saturation state for maintaining the memory circuit in an ON-state.