US 4,028,560 AGranted

Contact bounce transient pulse circuit eliminator

AssigneeMotorola, Inc.

InventorJames R. Bainter

Life of this patent

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Abstract

A circuit for eliminating transient pulses associated with the opening and closing of a mechanical contact by providing logic and memory circuit means for selectively comparing an input signal supplied from the contact terminal with the output signal from the memory means for either changing the state of the output signal or maintaining the output signal in its existing state. Only a single line connection to the contact terminal is required for supplying both the open and closed electrical signal representations of the contact position.

Claims5

Dependent claims

A circuit for eliminating contact bounce comprising:

a. a single line for transmitting input signals, said input signals comprising a first level and a second level and transient pulses associated therewith, said first and second levels being mutually distinct;
b. logic and memory circuit means having an input terminal and an output terminal, said input terminal being connected to said single line for receiving said input signal at time tO;
c. said logic and memory means being selectively responsive to said input signal for eliminating said transient pulses associated with either said first and second level and for generating a desired output signal level at time, tl, at said output terminal after a predetermined time period, T, said output signal level being representative of said input signal received at tO, where T = tl - tO;
d. said logic and memory circuit means further comprising a logic means and a memory means;
e. means for connecting said output terminal to said logic means and to said memory means;
f. said logic means being responsive to compare said input signals and said output signal levels for selectively generating first and second control signals;
g. means for connecting said first and second control signals to said memory means;
h. said memory means being selectively responsive to said first control signal for generating and storing a representation of said input signal and transmitting said representation signal to said output terminal after said predetermined time period, T, for changing the output signal level;
i. said memory means being selectively responsive to said second control signal for maintaining said output terminal at its existing output signal level;
j. said memory means further comprising a shift register having N stages, a serial input terminal, N parallel input terminals, and a serial-parallel write mode select terminal, said serial-parallel write mode select terminal being connected to said logic means;
k. said serial-parallel write mode select terminal being responsive to said first control signal for storing and shifting said representation signal through said N stages in a serial mode for changing said output signal level;
and
said serial-parallel write mode select terminal being responsive to said second control signal for writing the existing output signal level into said N stages for maintaining said output terminal at its existing output signal level.

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Dependencies are inferred from the claim text.

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Abstract

A circuit for eliminating contact bounce comprising:

a. a single line for transmitting input signals, said input signals comprising a first level and a second level and transient pulses associated therewith, said first and second levels being mutually distinct;
b. logic and memory circuit means having an input terminal and an output terminal, said input terminal being connected to said single line for receiving said input signal at time tO;
c. said logic and memory means being selectively responsive to said input signal for eliminating said transient pulses associated with either said first and second level and for generating a desired output signal level at time, tl, at said output terminal after a predetermined time period, T, said output signal level being representative of said input signal received at tO, where T = tl - tO;
d. said logic and memory circuit means further comprising a logic means and a memory means;
e. means for connecting said output terminal to said logic means and to said memory means;
f. said logic means being responsive to compare said input signals and said output signal levels for selectively generating first and second control signals;
g. means for connecting said first and second control signals to said memory means;
h. said memory means being selectively responsive to said first control signal for generating and storing a representation of said input signal and transmitting said representation signal to said output terminal after said predetermined time period, T, for changing the output signal level;
i. said memory means being selectively responsive to said second control signal for maintaining said output terminal at its existing output signal level;
j. said memory means further comprising a shift register having N stages, a serial input terminal, N parallel input terminals, and a serial-parallel write mode select terminal, said serial-parallel write mode select terminal being connected to said logic means;
k. said serial-parallel write mode select terminal being responsive to said first control signal for storing and shifting said representation signal through said N stages in a serial mode for changing said output signal level;
and
said serial-parallel write mode select terminal being responsive to said second control signal for writing the existing output signal level into said N stages for maintaining said output terminal at its existing output signal level.

10 more elements