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US 4,010,453 AGranted
Stored charge differential sense amplifier
AssigneeInternational Business Machines Corporation
InventorScott Clarence Lewis
Life of this patent
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AssigneeInternational Business Machines Corporation
InventorScott Clarence Lewis
Estimating the term…
A differential sense amplifier for semiconductor memory cells is described which uses charge transfer preamplification in combination with a ratioless cross-coupled latch circuit to provide sensing and regeneration of binary information stored in a charge storage device. The sense amplifier may be utilized in arrays of single FET/capacitor memory cells in which the sense amplifier is centrally located and data input/output connections are made at one outside edge of the array. Single bit line driving is made possible by the use of a bit decoder which unconditionally couples charge to a single bit line common mode charge coupling to decrease potentials on a pair of bit lines coupled to the sense amplifier. The common mode bit line discharge means also increases response of the charge transfer preamplifier stage. A single transmission gate device is used for both reading out from a single bit line and writing new data into a memory cell, thus simplifying the input/output circuitry. A sense node shunting device is utilized during the bit line precharge portion of the memory cycle to partially charge the bit sense line previously discharged to ground in order to conserve power and to ensure proper operation of the charge transfer preamplifier on the next memory cycle. In semiconductor memory applications where high performance is critical, the charge transfer preamplifier stage and common mode discharging circuit may be omitted and the bit lines connected directly to the sense nodes of a cross-coupled latching circuit without the loss of other benefits of the circuit.
In a memory system including a plurality of charge storage cells associated with first and second bit/sense lines coupled to a differential sense amplifier circuit, the improvement comprising:
In the memory system including first and second groups of charge storage means, each group being associated, respectively, with first and second bit/sense lines, the improvement comprising:
In a semiconductor memory array circuit including a plurality of charge storage means associated with a pair of bit/sense lines coupled to a differential sense amplifier, the improvement comprising
A semiconductor circuit comprising;
Dependencies are inferred from the claim text.