High speed divide-by-N circuit
AssigneeHughes Aircraft Company
InventorNorman E. Moyer
Life of this patent
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Abstract
Disclosed is a high speed divide-by-N circuit which uses both a synchronous down-counter and a ripple down-counter to obtain the advantages of each. The advantage of a ripple counter is that count propagation time is not critical, and the advantage of a synchronous counter is that its state can be decoded quickly. Therefore, by combining the two different types of counters, keeping the gate delays per clock cycle as low as possible, using look-ahead techniques, and giving more time-consuming operations more time to occur, a high speed divide-by-N circuit is obtained. Said circuit is intended for integration on a single chip, particularly using CMOS design and processing.
Claims10
A divide-by-N circuit comprising:
- an input clock;
- a synchronous down-counter for providing a high speed decode of a particular counter state;
- said synchronous down-counter having an output;
- a ripple down-counter, which is connected to and clocked by said output of said synchronous down-counter, for providing a counter of predetermined length, which is not required to quickly decode;
- a plurality of gates which provide a gated clock;
- said input clock being fed into said gates;
- and
- said gated clock being inputed into said synchronous counter.
Dependencies are inferred from the claim text.