First-in/first-out data storage system

A first-in/first-out data storage system alternatively operating in a read mode and a write mode, the system comprising:

• a shift register having a storage capacity of n stages in which data units can be stored;
• a modulo-n address counter having one state representing each stage of the shift register, the state of the address counter between operations indicating the number of stages of the shift register in which data units are stored;
• an input circuit;
• an output circuit;
• input switching means to transfer data units from the input circuit to the input of the shift register in a first state and to recirculate data units from the output of the shift register to the input of the shift register in a second state;
• output switching means to transfer data units from the output of the shift register to the output circuit in a first state and to recirculate data units from the output of the shift register to the input of the shift register in a second state;
• means during the read mode for placing the output switching means in the first state to transfer data units;
• means for shifting the data units stored in the shift register one stage and advancing the address counter one state for each data unit transferred during the read mode;
• means during the write mode for placing the input switching means in the first state the address counter is in a given state representing a full shift register, and placing the input switching means in the second state after the address counter is in the other states representing shift register stages in which data units are stored;
• and
• means for shifting the shift register n times and advancing the address counter n - 1 times for each data unit transferred during the write mode.

A binary data memory device from which data units are retrievable on a first-in/first-out basis, the memory device comprising:

• a shift register having a storage capacity of a given number of stages in which data units can be stored, the last data unit placed in the shift register being located at the input of the shift register and the remaining data units in the shift register being displaced from the input of the shift register in successive stages corresponding to the order of placement of such data units in the shift register;
• first means for shifting the data units stored in the shift register one state each time a new data unit is to be stored in the shift register;
• storing means for transferring the new data unit to the input of the shift register as the first shifting means shifts;
• second means for shifting the data units stored in the shift register the given number of stages each time a data unit is to be retrieved from the shift register;
• and
• retrieving means for transferring a data unit out of the output of the shift register when the first data unit placed in the shift register is at the output of the shift register and thereafter recirculating the successive data units to the input of the shift register as the second shifting means shifts, the retrieving means including an address counter having a number of states equal to the given number of stages of the shift register, one state of the address counter representing an empty shift register, means for advancing the address counter one state each time a new data unit is transferred to the input of the shift register, means as the second shifting means shifts for advancing the address counter one state for each shift until the state of the address counter represents an empty shift register and thereafter advancing the address counter one state for each shift except one, and means when the address counter assumes the state after the state representing an empty shift for transferring the data unit out of the output of the shift register.

A binary data memory device from which data units are retrievable on a first-in/first-out basis, the memory device comprising:

• a shift register having a storage capacity of n stages in which data units are stored, the first data unit placed in the shift register being located at the output of the shift register and the remaining data units in the shift register being displaced from the output of the shift register in successive stages corresponding to the order of placement of such data units in the shift register;
• first means for shifting the data units stored in the shift register one stage each time the first data unit is to be transferred out of the output of the shift register;
• retrieving means for transferring the first data unit out of the output of the shift register;
• second means for shifting the data units stored in the shift register n stages each time a new data unit is to be placed in the shift register;
• and
• storing means for transferring the new data unit to the input of the shift register when the last data unit placed in the shift register is at the input of the shift register and prior thereto recirculating the successive data units from the output of the shift register to the input of the shift register as the shift register shifts during placement of the new data unit, the storing means including an address counter having a number of states equal to the given number of stages of the shift register, one state of the address counter representing a full shift register, means for advancing the address counter one state each time the last data unit is transferred out of the output of the shift register, means as the second shifting means shifts for advancing the address counter one state for each shift until the state of the address counter represents a full shift register and thereafter advancing the address counter one state for each shift of the shift register except one, and means when the address counter assumes the state after the state representing a full shift register for transferring the data unit into the input of the shift register.

Data communication apparatus having a data receiver that generates a write request signal upon the acceptance of abbreviated data characters;

• a data analyzer for expanding the abbreviated data characters accepted by the data receiver one at a time into full text data characters, the data analyzer generating a read request signal after each abbreviated data character is expanded;
• and a teleprinter that produces written characters on paper responsive to data characters from the data analyzer;
• the improvement comprising a first-in/first-out memory device coupling the data receiver to the data analyzer, the memory device comprising:
• a shift register having a storage capacity of a given number of stages in which data characters can be stored, the last data character placed in the shift register being located at the input of the shift register and the remaining data characters in the shift register being displaced from the input of the shift register in successive stages corresponding to the order of placement of such data characters in the shift register;
• first means responsive to a write request for shifting the data characters stored in the shift register one stage each time a new data character is to be stored in the shift register;
• storing means for transferring the new data character from the data receiver to the input of the shift register as the first shifting means shifts;
• second means responsive to a read request for shifting the data characters stored in the shift register the given number of stages each time a data character is to be retrieved from the shift register;
• and
• retrieving means for transferring a data character from the output of the shift register to the data analyzer when the first data character placed in the shift register is at the output of the shift register and thereafter recirculating the successive data characters to the input of the shift register as the second shifting means shifts.