Charge effects in doped silicon dioxide
AssigneeBell Telephone Laboratories, Incorporated
InventorsDawon Kahng, Joseph Raymond Ligenza
Life of this patent
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Abstract
Charge conditions are modified in a wafer including a silicon dioxide layer on a silicon substrate by introducing a distribution of tantalum into the silicon dioxide layer. The distribution of tantalum can be adapted to store negative charge, to getter sodium or to produce nonannealable fast surface states. A distribution of tantalum at the silicon-silicon dioxide interface produces nonannealable fast surface states. A distribution of tantalum in the silicon dioxide subjected to electrical and temperature stress can store negative charge and getter sodium. An n-channel insulated gate field effect transistor utilizes a silicon dioxide gate insulator which includes centrally located therein a region which is rich in treated tantalum.
Claims12
A semiconductor device comprising a silicon semiconductor substrate of a first conductivity type, a pair of spaced impurity zones of a second conductivity type formed into the substrate, a layer of silicon dioxide contacting the substrate and overlying the space between the impurity zones, a layer of metal contacting the silicon dioxide layer, and having a distribution of tantalum in one of its oxidation states in the silicon dioxide layer, said distribution characterized by a peak in the silicon dioxide layer and by a concentration of tantalum in the silicon dioxide layer in the range between about 10.sup.13 and 1.5 .times. 10.sup.15 per square centimeter.
An insulated gate field effect transistor device comprising a silicon wafer which includes n-type source and drain zones separated by a p-type gate region
- characterized in that the gate insulator overlying the gate region consists of a silicon dioxide layer having within its bulk a sub-region which is rich in tantalum, said tantalum being in a distribution, substantially confined to the sub-region, which has a peak in said silicon dioxide layer, said distribution characterized by a concentration of tantalum in the range of about 10.sup.13 to 1.5 .times. 10.sup.15 per square centimeter.
An n-channel insulated gate field effect transistor device comprising a silicon wafer which includes source and drain zones separated by a gate region
- characterized by the improvement that the gate insulator overlying the gate region comprises a layer of genetic silicon dioxide which includes confined within its bulk a distribution of tantalum in a concentration of between about 10.sup.13 and about 10.sup.15 atoms per square centimeter forming a tantalum-rich region in the layer of silicon dioxide.
An insulated gate field effect transistor device comprising:
- a p-type silicon substrate,
- n-type source and drain zones formed into the silicon substrate and separated by a p-type gate region,
- a layer of genetic silicon dioxide about 1,000 A. thick overlying the p-type gate region,
- a layer of metal on the silicon dioxide layer, and
- a tantalum-rich region within the bulk of the silicon dioxide layer which includes tantalum in one of its oxidation states, said tantalum-rich region having a thickness, defined by inclusion of 75 percent of the tantalum in the oxide layer, of at least 100 A. in the direction normal to the interface of the layer of silicon dioxide and the silicon substrate, said tantalum-rich region being coextnsive with the gate region and having a peaked tantalum distribution, essentially Gaussian in shape, with a peak concentration in the range of about 5 .times. 10.sup.20 to about 3 .times. 10.sup.19 tantalum in one of its oxidation states per cubic centimeter, said peak being located at least 300 A. from the silicon-silicon dioxide interface.
Dependencies are inferred from the claim text.