Pulse pair recognition and relative time of arrival circuit
AssigneeElliott Brothers (London) Limited
InventorDennis Edwin Beeswing
Life of this patent
Estimating the term…
Abstract
A circuit arrangement for recognising two pulses in a series by their mutual separation and indicating the time of arrival of one of the pulses comprising a counter gated by the input signals which counts clock signals until a predetermined reference instant in time, a multiple shaft register which stores the binary count when the counter is inhibited and a serial shift register connected to receive the input signal and having along its length tappings spaced by an interval corresponding to a desired separation between the two input pulses, the tappings being connected to a coincidence gate which provides recognition pulses.
Claims19
A circuit arrangement for recognizing two pulses in a series which are separated in time by an amount equal to a certain number of periods of a selected frequency and for indicating the time of arrival of one of said pulses with reference to a recurrent timing signal occurring at said selected frequency, comprising in combination:
- first clock means for producing a recurrent timing signal at said selected frequency;
- a serial shift register having a plurality of stages, a data input connection for the first stage, output connections from two stages which are separated by a number of stages which is one less than said certain number of periods, and a shifting input connected to said recurrent timing signal;
- means connected to said output connections of said serial shift register for producing a recognizing signal in response to the presence of data simultaneously at said output connections;
- a multiple shift register having a series of parallel stages, count data inputs to the first of said parallel stages, count data outputs at the last of said parallel stages, and a shifting input connected to said recurrent timing signal;
- second clock means for producing a recurrent output signal at a frequency much higher than said selected frequency;
- and
- counter means for providing data input to said serial shift register and count data input to said multiple shift register in response to pulse input thereto, said counter means being connected to said output signal of the second clock means to count at said much higher frequency and having an input connection receiving said two pulses for initiation of counting, said counter means having a data output connected to said serial shift register in response to each of said two pulses and having a plurality of count outputs connected to said multiple shift register, whereby the count initiated by each of said two pulses up to the time of the timing signal next following each such pulse is shifted into said multiple shift register and through its succeeding stages in response to succeeding timing signals while data inputs to said serial shift register correspondingly are shifted into and through said serial shift register.
In a transponder system, a circuit for identifying response signals by their mutual separation in time and for measuring the time of arrival of one of the pulses in relation to a transmitted interrogation pulse, the circuit comprising:
- first clock means for generating first clock pulses of predetermined frequency,
- second clock means for generating second clock pulses having a frequency equal to a whole number multiple of the frequency of the first clock pulses,
- first counting means operative to count second clock pulses under the control of the response signals and the first clock pulses and to produce a count representative of the time of arrival of each response signal in relation to the repetition cycle of the first clock pulses,
- storage means for storing the counts of the first counting means,
- a multi-stage shifting register connected to receive as data input signals derived from the response signals and arranged to be stepped by the first clock pulses,
- coincidence gating means for detecting the simultaneous presence of signals in stages of the shift register spaced from one another by a time corresponding to the mutual separation of the response signals to be identified,
- second counting means operative to count clock pulses so as to measure the time interval between the transmission of the interrogation pulse and the appearance of a signal at the output of the coincidence gating means, and
- means for combining the count of the second counting means with the count stored in the storage means in respect of the response signal of which the time of arrival is to be measured.
In a circuit arrangement for recognizing two pulses in a series which are separated in time by an amount equal to a certain number of periods of a selected coarse frequency and for determining the time of arrival of one of said pulses with respect to a known reference time in units of a recurrent timing signal occurring at a fine frequency which is much greater than said selected frequency, in combination:
- first clock means for producing a recurrent timing signal at said fine frequency;
- second clock means for producing a recurrent output signal at said coarse frequency;
- signal generating means for producing a recognizing signal in response to a time separation between said pulses corresponding to said certain number of periods of said second clock means, the occurrence of said recognizing signal being in fixed time relation to a known cycle of said second clock means;
- a multiple shift register having a series of parallel stages, count data inputs to the first of said parallel stages, count data outputs at the last of said parallel stages, and a shifting input connected to said output signal of the second clock means;
- counter means for providing data input to said signal generating means and count data input to said multiple shift register in response to pulse input thereto, said counter means being connected to said output signal of the first clock means to count at said selected frequency and having an input connection receiving said two pulses for initiation of counting, said counter means having a data output connected to said signal generating means and having a plurality of count outputs connected to said multiple shift register;
- said multiple shift register having a number of stages such that the count data corresponding to all of said pulses is present in the last of said parallel stages when said recognizing signal is generated.
In a range computing system aboard an aircraft, in combination:
- clock means for generating fine clock pulses of a high frequency and coarse clock pulses of a low frequency, the frequency of said coarse clock pulses being a whole number division of the frequency of said fine clock pulses and being synchronized therewith;
- an input terminal for receiving pulse pairs transmitted by a ground beacon in response to interrogation by the aircraft;
- counter means connected to said input terminal and to said fine clock pulses for counting fine clock pulses subsequent to reception of each pulse of said pair;
- storage means connected to said counter means and to said coarse clock pulses for capturing the count of said counter means when known cycles of said coarse clock pulses occur;
- signal generating means connected to said counter means and to said coarse clock pulses for producing a recognizing signal in response to a predetermined time separation between the pulses of said pair which corresponds to the aircraft, the occurrence of said recognizing signal being in fixed time relation to said known cycles of said coarse clock pulses;
- a second counter means connected to said coarse clock pulses for counting coarse clock pulses subsequent to interrogation;
- and
- latch means connected to said storage means and to said second counter means for recovering the count from said storage means which corresponds to one of the pulses of said pair and for capturing the count of said second counter means when said recognizing signal occurs, whereby the time delay between interrogation and the reception of said one pulse of said pair may be determined.
In a transponder system aboard an aircraft, in combination:
- clock means for generating fine clock pulses and coarse clock pulses, the coarse clock pulses being synchronized with the fine clock pulses and occurring at a frequency much less than the frequency of said fine clock pulses;
- an input terminal receiving a pair of response pulses transmitted by a ground beacon in response to interrogation by the aircraft;
- signal generating means for recognizing a particular time separation between said pair of response pulses and for generating a recognizing signal in response thereto, said signal generating means being driven by said coarse clock pulses whereby an unknown time delay occurs between response pulse reception and input to said signal generating means whereas a predetermined time delay occurs between input to said signal generating means and generation of said recognizing signal;
- and
- means for determining said unknown time delay comprising counter means connected to said input terminal and to said fine clock pulses for counting fine clock pulses beginning at each response pulse reception and storage means connected to said coarse clock pulses for capturing the count of said counter means in synchronism with said coarse clock pulses, the captured count associated with one of said response pulses being available at the time of generation of said recognizing signal.
Dependencies are inferred from the claim text.