Data processing unit having a plurality of hardware circuits for processing data at different priority levels

In a data processing unit of the type having a plurality of hardware data processing circuits for processing data at corresponding priority levels, a memory for storing microinstructions and, for each of said priority levels a program counter register for addressing in succession said microinstructions, wherein the improvement comprises:

• means controlled by a level change signal defined by a predeterined microinstruction executed by the circuits of a predetermined priority level for switching said unit from said predetermined level to a lower priority level, said predetermined microinstruction comprising a first character code for defining the priority level change microinstruction and a second character code for specifying an address;
• a first register included in said data processing unit for storing said first character code;
• a control unit connected to said first register for decoding said first character code and for generating a plurality of control signals in accordance with said predetermined microinstruction defined by said first character code;
• means responsive to said control signals for transferring the content of the program counter register of said lower priority level into a predetermined location of said memory;
• and
• means responsive to said control signals for storing the address specified by said second character code into said program counter register of said lower priority level.