Information processing device for processing instructions including branch instructions

An information processing device comprising, in combination:

• a route memory which includes
• route index memory means for storing branch target addresses of a plurality of branch target instructions, and
• route buffer memory means for storing branch target instructions at the corresponding branch target addresses stored in said route index memory;
• instruction unit means for picking up and decoding an instruction to be processed;
• referencing means, connected to said instruction unit and said route memory, for referencing the route index memory means by the address of the instruction to be processed from said instruction unit means when the decoding of the instruction is started by said instruction unit means, to detect the branch target address in said route index memory means coincident with the address of the instruction to be processed;
• and
• read-out means, connected to said route memory and said instruction unit means, for reading out the branch target instruction corresponding to the branch target address detected by said referencing means and for transferring the branch target instruction read-out from said route buffer memory means to said instruction unit means.