Semiconductor package

A semiconductor package comprising:

• a package substrate;
• a first chip stack structure comprising a plurality of first semiconductor chips offset-stacked in a first direction on the package substrate;
• a plurality of first semiconductor chip pads in parallel and spaced apart from each other in a second direction on an upper surface of each of the plurality of first semiconductor chips;
• a second chip stack structure offset-stacked in the first direction and a second direction on an upper surface of an uppermost first semiconductor chip of the plurality of first semiconductor chips, the second chip stack structure comprising a plurality of second semiconductor chips that are offset-stacked in the first direction;
• a plurality of second semiconductor chip pads spaced apart from each other in the second direction on an upper surface of each of the plurality of second semiconductor chips;
• a plurality of substrate pads arranged in a first row and a second row on the package substrate;
• a plurality of conductive patterns connecting (i) one or more respective first semiconductor chip pads of the plurality of the first semiconductor chip pads to one or more respective substrate pads of the plurality of substrate pads and (ii) one or more respective second semiconductor chip pads of the plurality of second semiconductor chip pads to one or more respective substrate pads of the plurality of substrate pads;
• and
• an insulating pattern positioned between respective conductive patterns of the plurality of conductive patterns facing each other in a vertical direction,
• wherein the plurality of substrate pads comprise a plurality of ground/power substrate pads and a plurality of signal substrate pads,
• wherein the plurality of ground/power substrate pads and the plurality of signal substrate pads are alternately positioned in each of the first row and the second row,
• wherein the plurality of ground/power substrate pads face each other diagonally when viewed from above in the vertical direction, and
• wherein the plurality of signal substrate pads face each other diagonally when viewed from above in the vertical direction.

A semiconductor package comprising:

• a package substrate;
• a first chip stack structure comprising a plurality of first semiconductor chips offset-stacked in a first direction on the package substrate,
• a plurality of first semiconductor chip pads in parallel and spaced apart from each other in a second direction on an upper surface of each of the plurality of first semiconductor chips,
• a second chip stack structure offset-stacked in each of the first direction and a second direction perpendicular to the first direction, on an upper surface of an uppermost first semiconductor chip of the plurality of first semiconductor chips, the second chip stack structure comprising a plurality of second semiconductor chips offset-stacked in the first direction;
• a plurality of second semiconductor chip pads spaced apart from each other in the second direction on a top surface of each of the plurality of second semiconductor chips;
• a plurality of substrate pads arranged in a first row and a second row on the package substrate;
• a plurality of conductive patterns connecting the first semiconductor chip pad to the substrate pads and the second semiconductor chip pad to the substrate pads;
• and
• an insulating pattern between respective conductive patterns of the plurality of conductive patterns facing each other in a vertical direction,
• wherein the plurality of substrate pads comprise a plurality of ground/power substrate pads and a plurality of signal substrate pads that are alternately positioned in each of a first row and a second row,
• wherein the plurality of ground/power substrate pads face each other diagonally when viewed from above in the vertical direction,
• wherein the plurality of signal substrate pads face each other diagonally when viewed from above in the vertical direction,
• wherein the plurality of conductive patterns comprise a plurality of ground/power conductive patterns and a plurality of signal conductive patterns that are alternately positioned,
• wherein respective substrate pads of the plurality of substrate pads in the first row overlap the plurality of first semiconductor chip pads in the first direction,
• wherein respective substrate pads of the plurality of substrate pads in the second row overlap the plurality of second semiconductor chip pads in the first direction, and
• wherein at least one of the respective substrate pads in the first row does not overlap at least one of the respective substrate pads in the second row in the first direction.