Semiconductor package with stress-relief structures
AssigneeSamsung Electronics Co., Ltd.
InventorHyejin KIM
Life of this patent
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Abstract
Provided is a semiconductor package including: a package substrate; an interposer substrate on a first surface of the package substrate; a first connection terminal between the package substrate and the interposer substrate; a first semiconductor device on the interposer substrate; and a second semiconductor device on the interposer substrate, wherein the second semiconductor device is spaced apart from the first semiconductor device in a horizontal direction, wherein the package substrate includes a first dummy hole extending in a vertical direction from the first surface of the package substrate, and wherein a distance from an edge of the package substrate adjacent to the first dummy hole is less than a distance from the edge to the first connection terminal.
Claims20
A semiconductor package comprising:
- a package substrate;
- an interposer substrate on a first surface of the package substrate;
- a first connection terminal between the package substrate and the interposer substrate;
- a first semiconductor device on the interposer substrate;
- and
- a second semiconductor device on the interposer substrate,
- wherein the second semiconductor device is spaced apart from the first semiconductor device in a horizontal direction,
- wherein the package substrate comprises a first dummy hole extending in a vertical direction from the first surface of the package substrate, and
- wherein a distance from an edge of the package substrate adjacent to the first dummy hole is less than a distance from the edge to the first connection terminal.
A semiconductor package comprising:
- a package substrate comprising an internal area and an edge area surrounding the internal area;
- an interposer substrate on a first surface of the package substrate, the interposer substrate comprising a capacitor;
- a first connection terminal between the package substrate and the interposer substrate;
- a first semiconductor device on the interposer substrate;
- and
- a second semiconductor device on the interposer substrate,
- wherein the first semiconductor device and the second semiconductor device are spaced apart in a horizontal direction,
- wherein the package substrate further comprises a first dummy hole in the edge area, the first dummy hole extending in a vertical direction from the first surface of the package substrate, and
- wherein the interposer substrate further comprises a second dummy hole between the first semiconductor device and the second semiconductor device in a top view, the second dummy hole extending in the vertical direction from an upper surface of the interposer substrate.
A semiconductor package comprising:
- a package substrate comprising:
- a core layer;
- an internal area;
- and an edge area;
- an interposer substrate on a first surface of the package substrate, the interposer substrate having a horizontal width less than a horizontal width of the package substrate;
- a first connection terminal connecting the interposer substrate and the package substrate in the internal area;
- a first semiconductor device and a second semiconductor device on the interposer substrate, the first semiconductor device and the second semiconductor device arranged in a horizontal direction;
- a second connection terminal between the interposer substrate and the first semiconductor device;
- and
- a third connection terminal between the interposer substrate and the second semiconductor device,
- wherein the package substrate further comprises;
- a first dummy hole in the edge area, the first dummy hole extending in a vertical direction from the first surface of the package substrate;
- and
- a second dummy hole in the internal area, the second dummy hole extending in the vertical direction from the first surface of the package substrate,
- wherein the interposer substrate comprises a third dummy hole between the second connection terminal and the third connection terminal, the third dummy hole extending in the vertical direction from an upper surface of the interposer substrate, and
- wherein the first dummy hole and the second dummy hole are spaced apart from the core layer.
Dependencies are inferred from the claim text.