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US 2026/0314381 A1Published application
Semiconductor device
AssigneeFujian Jinhua Integrated Circuit Co., Ltd.
InventorsYidan ZHANG, Yifei YAN, Anping ZENG, Jianshan WU, Erpeng ZHUANG
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Abstract
The application provides a semiconductor device applied to semiconductor technical field. In the application, insulating capping layer structures are arranged in some components of the semiconductor device, respectively, and portions of the insulating capping layer structures extend into the components, respectively, thereby proposing a new structure and improving the reliability and performance of semiconductor devices.
Claims20
A semiconductor device, comprising:
- a substrate;
- a plurality of bit lines, arranged on the substrate and spaced apart from each other along a horizontal direction;
- a plurality of spacers, located on side walls of the bit lines respectively;
- a plurality of insulating capping layer structures, covering the plurality of bit lines and the spacers, wherein each insulating capping layer structure comprises a first portion arranged on the bit line and a second portion located within the spacer;
- a plurality of pad structures, wherein each pad structure is located between adjacent bit lines, covers a portion of a side wall of the spacer, and in direct contact with a top surface of the insulating capping layer structure.
2 more elements
A semiconductor device, comprising:
- a substrate, comprising a plurality of active regions defined by trench isolations;
- a plurality of bit lines, arranged on the substrate and spaced apart from each other along a horizontal direction;
- wherein each bit line comprise a metal layer and an insulating layer formed in sequence from bottom to top;
- a plurality of spacers, wherein each spacer comprises a first spacer, a second spacer, and a third spacer stacked in sequence, arranged on the opposite side walls of the bit line;
- a plurality of insulating capping layer structures, wherein each insulating capping layer structure simultaneously contacts a top of the insulating layers of the bit lines, a top and a side wall of the first spacers, a top of the second spacer, and a top and a side wall of the third spacer, wherein a portion of the insulating capping layer structure in direct contact with the second spacer has a lowest bottom surface;
- a plurality of pad structures, wherein each pad structure is located between adjacent bit lines, covers a portion of a side wall of the spacer, and in direct contact with top surface of the insulating capping layer structure.
3 more elements
Dependencies are inferred from the claim text.