Machine learning-based product test-time reduction for test flow, manufacture, design, and operation of integrated-circuit devices
AssigneeNXP B.V.
InventorsMehul D. Shroff, Nguyen Nguyen
Life of this patent
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Abstract
A method, apparatus, and system for fabricating and testing integrated-circuit (IC) devices include providing an IC device containing circuitry for performing electrical functions of the IC device, and then applying a plurality of tests to the circuitry to test the electrical functions of the IC device, where the plurality of tests is generated with a test-time reduction methodology, which uses a combination of association-analysis processing and greedy-algorithm processing to evaluate fail-test data from an input test dataset to identify and eliminate redundant or unnecessary tests from the input test dataset to generate the plurality of tests.
Claims20
A method for fabricating integrated circuit devices, comprising:
- providing an integrated-circuit (IC) device containing circuitry;
- and
- applying a plurality of tests to the circuitry to test electrical functions of the IC device, where the plurality of tests is generated with a test-time reduction methodology that uses association-analysis processing to evaluate fail-test data from an input test dataset to identify and eliminate redundant or unnecessary tests from the input test dataset when generating the plurality of tests.
A system of identifying a plurality of tests to test one or more electrical functions of an integrated-circuit (IC) device, the system comprising:
- an electronic processing system configured to:
- receive an input test dataset listing of a plurality of tested IC devices with one or more fail test IDs for each fail test applied to each tested IC device;
- apply association-analysis processing to evaluate fail tests in the input test dataset to identify a one or more first fail test removal recommendations and fail test keep recommendations;
- and
- remove the recommended redundant fail tests from the input test dataset to generate the plurality of tests.
A method for identifying a plurality of tests to test one or more electrical functions of an integrated-circuit (IC) device, comprising:
- receiving an input test dataset listing of a plurality of tested IC devices with one or more fail-test IDs for each fail test applied to each tested IC device;
- applying association-analysis processing to evaluate fail tests in the input test dataset to identify a one or more first fail-test removal recommendations and fail test keep recommendations;
- applying greedy-algorithm processing to evaluate fail tests in the input test dataset to identify a one or more second fail-test removal recommendations and fail test keep recommendations;
- resolving conflicts between the one or more first fail-test removal recommendations and the one or more second fail-test removal recommendations to identify recommended redundant fail tests from the input test dataset;
- and
- removing the recommended redundant fail tests from the input test dataset to generate the plurality of tests.
Dependencies are inferred from the claim text.