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US 2026/0314044 A1Published application
Top source drain and assocated ild formation within a stacked transistor
AssigneeInternational Business Machines Corporation
InventorsEunsoo Cho, Ruilong Xie, Thanh Nguyen, Shay Reboh, Kamal Rudra, Shravana Kumar Katakam, Ashim Dutta
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Abstract
A stacked transistor is presented. The stacked transistor includes a top source/drain (S/D) region that has a lower portion and an upper portion. The stacked transistor includes a bottom interlayer dielectric (ILD) in contact with the lower portion of the top S/D region. The stacked transistor includes a top ILD in contact with the upper portion of the top S/D region.
Claims20
A stacked transistor comprising:
- a top source/drain (S/D) region comprising a lower portion and an upper portion;
- a bottom S/D region below the top S/D region;
- a bottom interlayer dielectric (ILD) in contact with the bottom S/D region and in contact with the lower portion of the top S/D region;
- and
- a top ILD in contact with the upper portion of the top S/D region.
2 more elements
A stacked transistor comprising:
- a top source/drain (S/D) region comprising a lower portion and an upper portion;
- a bottom interlayer dielectric (ILD) in contact with the lower portion of the top S/D region;
- and
- a top ILD in contact with the upper portion of the top S/D region.
1 more element
A stacked transistor comprising:
- a bottom source/drain (S/D) region;
- a top S/D region that is offset from the bottom S/D region, the top S/D region comprising a lower portion that is inset relative to an upper portion;
- and
- an interlayer dielectric (ILD);
- wherein the upper portion of the top S/D region comprises a bottom surface that is substantially coplanar with a top surface of the ILD.
2 more elements
Dependencies are inferred from the claim text.