Semiconductor structure and method for manufacturing the same

A method comprising:

• forming a gate dielectric layer over a first channel region and a second channel region;
• forming a first dipole layer over the gate dielectric layer over the first channel region;
• forming a blocking layer over the first dipole layer, the blocking layer having a thickness;
• forming a second dipole layer over the blocking layer over the first channel region and over the gate dielectric layer over the second channel region;
• and
• annealing to drive first dipole dopants from the first dipole layer into the gate dielectric layer over the first channel region and second dipole dopants from the second dipole layer into the gate dielectric layer over the second channel region, the second dipole dopants diffusing into the blocking layer to a depth less than the thickness of the blocking layer.

A method comprising:

• forming a gate dielectric layer over a first channel region and a second channel region;
• forming a first dipole layer over the gate dielectric layer over the first channel region, the first dipole layer having an edge facing the second channel region;
• forming a second dipole layer over the gate dielectric layer over the second channel region and over the first dipole layer in the first channel region, the second dipole layer having an edge facing the first channel region;
• and
• annealing to drive a first dipole dopant from the first dipole layer into the gate dielectric layer over the first channel region and a second dipole dopant from the second dipole layer into the gate dielectric layer over the second channel region, the annealing further driving the first dipole dopant and the second dipole dopant into an overlap region of the gate dielectric layer between the first channel region and the second channel region such that the overlap region contains both the first dipole dopant and the second dipole dopant.