Gate structure for semiconductor device

A semiconductor device, comprising:

• a substrate;
• a first source/drain region disposed on a first base structure on the substrate;
• a second source/drain region disposed on a second base structure on the substrate;
• first and second stacks of nanostructured channel regions disposed on the first and second base structures, respectively;
• a gate structure disposed on the first and second stacks of nanostructured channel regions;
• and
• an isolation structure comprising first and second isolation portions, wherein:
• the first isolation portion is disposed between the first and second source/drain regions,
• the second isolation portion is disposed on the first isolation portion and is surrounded by the gate structure, and
• a bottom surface of the second isolation portion is at a surface plane above top surfaces of the first and second stacks of nanostructured channel regions.

A semiconductor device, comprising:

• a substrate;
• first, second, and third source/drain regions disposed on first, second, and third base structures, respectively, on the substrate;
• a gate structure disposed on the substrate and comprising a gate dielectric layer and a gate electrode layer;
• a first isolation structure, comprising:
• a bottom isolation portion disposed between the first and second source/drain regions;
• a top isolation portion disposed on the bottom isolation portion and vertically extending above the gate electrode layer;
• and
• a second isolation structure disposed between the second and third source/drain regions and under the gate electrode layer.