Semiconductor memory device, method for fabricating the same and electronic system including the same

A method for manufacturing a semiconductor memory device, the method comprising:

• forming a preliminary mold on a cell substrate, the preliminary mold including mold insulating layers and mold sacrificial layers alternately stacked;
• forming a channel hole penetrating the preliminary mold in a vertical direction crossing an upper surface of the cell substrate;
• performing a first recess process on the mold insulating layers exposed by the channel hole to cause a portion of the mold sacrificial layers to protrude toward the channel hole;
• forming a blocking insulating pattern by performing a first oxidation process on at least the portion of the mold sacrificial layers protruding toward the channel hole;
• forming a preliminary charge storage layer on the mold insulating layers and the blocking insulating pattern in the channel hole;
• forming a mask pattern on the preliminary charge storage layer on a side surface of the blocking insulating pattern;
• forming a charge storage layer by performing a second oxidation process on the preliminary charge storage layer by using the mask pattern, the charge storage layer including a charge trap portion extending along the side surface of the blocking insulating pattern and a first charge blocking portion extending along a side surface of each of the mold insulating layers;
• forming a tunnel insulating layer and a semiconductor layer on the charge storage layer in the channel hole sequentially;
• and
• forming a mold stack including the mold insulating layers and gate electrodes by replacing the mold sacrificial layers with the gate electrodes,
• wherein an oxygen concentration of the first charge blocking portion is higher than an oxygen concentration of the charge trap portion.

A method for manufacturing a semiconductor memory device, the method comprising:

• forming a preliminary mold on a cell substrate, the preliminary mold including mold insulating layers and mold sacrificial layers alternately stacked;
• forming a channel structure penetrating the preliminary mold in a vertical direction crossing an upper surface of the cell substrate;
• and
• forming a mold stack including the mold insulating layers and gate electrodes by replacing the mold sacrificial layers with the gate electrodes,
• wherein forming the channel structure comprises:
• forming a channel hole penetrating the preliminary mold in a vertical direction crossing an upper surface of the cell substrate;
• forming a recess on the mold insulating layers exposed by the channel hole to cause a portion of the mold sacrificial layers to protrude toward the channel hole;
• forming a blocking insulating pattern by performing a first oxidation process on at least the portion of the mold sacrificial layers protruding toward the channel hole;
• forming a preliminary charge storage layer on the mold insulating layers and the blocking insulating pattern in the channel hole;
• forming a mask pattern on the preliminary charge storage layer on a side surface of the blocking insulating pattern;
• forming a charge storage layer by performing a second oxidation process on the preliminary charge storage layer by using the mask pattern, the charge storage layer including a charge trap portion and a first charge blocking portion alternately arranged in the vertical direction;
• and
• forming a tunnel insulating layer and a semiconductor layer on the charge storage layer in the channel hole sequentially,
• wherein the charge trap portion is between the semiconductor layer and the blocking insulating pattern,
• wherein the first charge blocking portion is between the semiconductor layer and each of the mold insulating layers, and
• wherein an oxygen concentration of the first charge blocking portion is higher than the oxygen concentration of the charge trap portion.