Method for Forming a Memory Structure for a 3D NAND Flash Memory

A method, comprising:

• forming a layer stack over a substrate, wherein the layer stack comprises an alternating sequence of gate layers and inter-gate spacer layers;
• forming recessed areas in a sidewall surrounding a memory hole in the layer stack by laterally etching back the gate layers relative to the inter-gate spacer layers from the memory hole to produce a plurality of etched-back gate layers;
• for each of the recessed areas, forming a blocking oxide layer, wherein a thickness of each blocking oxide layer in a lateral direction is less than a depth of the recessed area in the lateral direction;
• conformally depositing a liner layer on exposed surfaces in the memory hole, wherein the liner layer covers the blocking oxide layer in each of the recessed areas;
• depositing a sacrificial layer on the liner layer;
• etching back the sacrificial layer such that the liner layer is exposed outside the recessed areas and discrete portions of the sacrificial layer remain in the recessed areas;
• removing exposed portions of the liner layer while using the discrete portions of the sacrificial layer as an etch mask such that discrete portions of the liner layer covered by the discrete portions of the sacrificial layer remain in each of the recessed areas;
• for each of the recessed areas, removing the discrete portions of the sacrificial layer;
• for each of the recessed areas, forming a charge trap layer, wherein the charge trap layer is deposited on the discrete portions of the liner layer remaining in the recessed area by a first area-selective deposition process while using the discrete portions of the liner layer as a seeding layer;
• subsequent to forming the charge trap layers, depositing a tunnelling oxide layer in the memory hole;
• and
• depositing a channel layer on the tunnelling oxide layer.