Microelectronic devices and related memory devices

A microelectronic device, comprising:

• a memory array region comprising stack structures horizontally extending in parallel in a first direction and separated from one another in a second direction orthogonal to the first direction, the stack structures individually comprising local word line (LWL) structures vertically stacked relative to one another;
• a global word line (GWL) region comprising GWL structures vertically extending across an entire vertical span of the stack structures of the memory array region;
• and
• a word line select (WLSEL) region horizontally interposed between the memory array region and the GWL region in the first direction, the WLSEL region comprising vertical stacks of sub-word line driver (SWD) devices individually coupled to, vertically overlapping, and horizontally extending between one of GWL structures of the GWL region and the LWL structures of one of the stack structures of the memory array region.

A memory device, comprising:

• a stack structure comprising local word line (LWL) structures vertically stacked relative to one another and substantially linearly horizontally extending in a first direction;
• vertical stacks of volatile memory cells within a vertical extent of and individually operatively connected to the LWL structures of the stack structure;
• a global word line (GWL) structure continuously vertically extending across all of the LWL structures of the stack structure, the GWL structure horizontally overlapping the stack structure in a second direction perpendicular to the first direction;
• and
• a vertical stack of sub-word line driver (SWD) devices horizontally interposed between the GWL structure and the stack structure in the first direction and horizontally overlapping the GWL structure and the stack structure in the second direction, the vertical stack of SWD devices comprising SWD devices at vertical elevations of the LWL structures of the stack structure and individually coupled to the GWL structure and a respective one of the LWL structures.