Memory array, memory, and electronic device

A storage array, comprising:

• a substrate;
• a plurality of storage layers stacked on the substrate along a first direction perpendicular to the substrate;
• each of the plurality of storage layers includes a plurality of storage cells and a first control line structure,
• wherein each of the plurality of storage cells includes a floating body effect transistor, and the floating body effect transistor includes a first gate, a first electrode, a second electrode, and a channel located between the first electrode and the second electrode, the channel being arranged along a second direction parallel to the substrate, and the first gate being separated from the channel by a gate oxide dielectric layer;
• and
• wherein each of the plurality of storage layers further includes a plurality of second control line structures and a third control line structure, the first electrode of each floating body effect transistor being connected to the first control line structure, the second electrode being connected to the second control line structure, and the first gate being connected to the third control line structure.