US 2026/0313868 A1Published application

Manufacturing method of a capacitor-less memory device

AssigneePostech Research and Business Development Foundation

InventorsDae Hwan KANG, Yong Woo RYU, Gyu Heon BAE

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Abstract

A manufacturing method of a capacitor-less memory device includes stacking a plurality of first semiconductor layers on a substrate to be spaced apart from each other, forming a plurality of first gate electrode layers, forming a plurality of first gate insulating layers, forming at least one pair of first trenches, forming a plurality of back gate electrode layers, forming a plurality of first drain electrode layers, forming a plurality of first source electrode layers and a plurality of second gate electrode layers, forming a plurality of second semiconductor layers, forming a plurality of second gate insulating layers, forming a bit line, forming a plurality of word lines, and forming a plurality of control lines.

Claims19

Dependent claims

A manufacturing method of a capacitor-less memory device, comprising:

forming a plurality of first semiconductor layers stacked on a substrate so as to be spaced apart from each other, a plurality of first gate electrode layers disposed between the plurality of first semiconductor layers, and a plurality of first gate insulating layers disposed between the plurality of first semiconductor layers and the plurality of first gate electrode layers;
patterning the plurality of first semiconductor layers, the plurality of first gate electrode layers, and the plurality of first gate insulating layers to form at least one pair of first trenches;
removing the first semiconductor layers between the pair of first trenches, and forming a plurality of back gate electrode layers in portions from which the first semiconductor layers have been removed, the plurality of back gate electrode layers being insulated from the plurality of first gate electrode layers;
forming a plurality of first drain electrode layers so as to be connected respectively to one side of the plurality of first semiconductor layers;
forming a plurality of first source electrode layers and a plurality of second gate electrode layers so as to be connected respectively to the other side of the plurality of first semiconductor layers;
forming a plurality of second semiconductor layers extending vertically between the plurality of second gate electrode layers and the plurality of back gate electrode layers;
forming a bit line connected to the plurality of first drain electrode layers and connected to an upper end of the plurality of second semiconductor layers;
forming a plurality of word lines so as to be connected respectively to the plurality of first gate electrode layers;
and
forming a plurality of control lines so as to be connected respectively to the plurality of back gate electrode layers.

7 more elements

A manufacturing method of a capacitor-less memory device, comprising:

stacking a plurality of first semiconductor layers on a substrate so as to be spaced apart from each other;
forming a plurality of first gate electrode layers so as to be disposed between the plurality of first semiconductor layers;
forming a plurality of first gate insulating layers so as to be disposed between the plurality of first semiconductor layers and the plurality of first gate electrode layers;
patterning the plurality of first semiconductor layers, the plurality of first gate electrode layers, and the plurality of first gate insulating layers to form at least one pair of first trenches;
removing the first semiconductor layers between the pair of first trenches, and forming a plurality of back gate electrode layers in portions from which the first semiconductor layers have been removed, the plurality of back gate electrode layers being insulated from the plurality of first gate electrode layers;
removing one side of the plurality of first semiconductor layers by a predetermined amount, and then filling a conductive material in the removed portions so as to be connected respectively to one side of the plurality of first semiconductor layers, thereby forming a plurality of first drain electrode layers;
removing the other side of the plurality of first semiconductor layers by a predetermined amount, and then filling a conductive material in the removed portions so as to be connected respectively to the other side of the plurality of first semiconductor layers, thereby forming a plurality of first source electrode layers and a plurality of second gate electrode layers;
forming a plurality of second semiconductor layers extending vertically between the plurality of second gate electrode layers and the plurality of back gate electrode layers;
forming a plurality of second gate insulating layers between the plurality of second gate electrode layers and the plurality of second semiconductor layers and between the plurality of back gate electrode layers and the plurality of second semiconductor layers;
forming a bit line connected to the plurality of first drain electrode layers and connected to upper ends of the plurality of second semiconductor layers;
forming a plurality of word lines so as to be connected respectively to the plurality of first gate electrode layers;
and
forming a plurality of control lines so as to be connected respectively to the plurality of back gate electrode layers.

10 more elements

Dependencies are inferred from the claim text.