Multi-rate sigma-delta adc
AssigneeSemtech Corporation
InventorsEric Vandel, Aravind Prasad Heragu Singaiyengar
Life of this patent
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Abstract
A sigma-delta ADC for processing an analog input signal and generating a sampled digital representation of the input signal, comprising: a continuous-time subcircuit comprising an input integrator receiving the analog input signal and generating a first signal, a fast discrete-time subcircuit operating at a first clock rate receiving the first signal and generating a second signal, a slow discrete-time subcircuit operating according to a second clock rate slower than the first clock rate, the slow discrete-time subcircuit comprising a quantizer transforming the second signal into a digital signal and a DAC generating an analog feedback signal.
Claims8
A multi-rate continuous-time and discrete-time sigma-delta ADC for processing an analog input signal and generating a sampled digital representation of the input signal, comprising
- a continuous-time subcircuit comprising an input integrator receiving the analog input signal and generating a first signal
- a fast discrete-time subcircuit operating at a first clock rate receiving the first signal and generating a second signal
- a slow discrete-time subcircuit operating according to a second clock rate slower than the first clock rate, the slow discrete-time subcircuit comprising
- a quantizer transforming the second signal into a digital signal
- a DAC generating an analog feedback signal
Dependencies are inferred from the claim text.