Electrostatic discharge (esd) protection circuit using tie-cell technique

An integrated circuit, comprising:

• a pre-driver, coupled between a first voltage supply node, a reference voltage supply node;
• a switch device, coupled to the pre-driver;
• a post-driver, coupled between a second voltage supply node and the reference voltage supply node, and coupled to the pre-driver through the switch device;
• an input/output (I/O) pad, coupled to the post-driver;
• and
• a detection circuit, coupled between the second voltage supply node and the reference voltage supply node, and configured to generate a first control signal and a second control signal to selectively activate or deactivate the switch device in response to the integrated circuit being in a normal operation mode or an electrostatic discharge (ESD) mode,
• wherein the detection circuit comprises:
• a first transistor, having a gate terminal coupled to a first node, a first terminal coupled to the second voltage supply node, and a second terminal coupled to a second node;
• a first capacitor, coupled between the second voltage supply node and the first node;
• a second transistor, having a gate terminal coupled to the second node, a first terminal coupled to the first node, and a second terminal coupled to the reference voltage supply node;
• and
• a second capacitor, coupled between the second node and the reference voltage supply node.

A method, comprising:

• in response to an integrated circuit in an electrostatic discharge (ESD) mode, deactivating a switch device coupled between a pre-driver and a post-driver of the integrated circuit based on a first control signal and a second control signal generated by a detection circuit of the integrated circuit;
• and
• suppressing a voltage difference across a victim transistor of the post-driver in response to an ESD event occurring on an input/output pad of the integrated circuit in the ESD mode,
• wherein the detection circuit comprises:
• a first transistor, having a gate terminal coupled to a first node, a first terminal coupled to a voltage supply node, and a second terminal coupled to a second node;
• a first capacitor, coupled between the voltage supply node and the first node;
• a second transistor, having a gate terminal coupled to the second node, a first terminal coupled to the first node, and a second terminal coupled to a reference voltage supply node;
• and
• a second capacitor, coupled between the second node and the reference voltage supply node.