US 2026/0311743 A1 · PERIPHERAL CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME

Abstract

A memory device includes a cell array having first and second sub cell arrays, and first and second bit line sense amplifiers connected, respectively, to the first and second sub cell arrays. The memory device also includes first and second local I/O line pairs electrically connected, respectively, to a first bit line pair connected to the first bit line sense amplifier and a second bit line pair connected to the second bit line sense amplifier. The memory device further includes a common local I/O line pair connected to the first and second local I/O line pairs, a common local sense amplifier configured to amplify a voltage level transferred from the common local I/O line pair, a global I/O line pair connected to the common local sense amplifier, and an I/O sense amplifier electrically connected to the global I/O line pair.

Claims20

Dependent claims

A memory device, comprising:

a cell array including a first sub cell array and a second sub cell array;
a first bit line sense amplifier connected to the first sub cell array;
a second bit line sense amplifier connected to the second sub cell array;
a first local input/output (I/O) line pair electrically connected to a first bit line pair connected to the first bit line sense amplifier;
a second local I/O line pair electrically connected to a second bit line pair connected to the second bit line sense amplifier;
a common local I/O line pair connected to the first local I/O line pair and the second local I/O line pair;
a common local sense amplifier configured to amplify a voltage level transferred from the common local I/O line pair;
a global I/O line pair connected to the common local sense amplifier;
and
an I/O sense amplifier electrically connected to the global I/O line pair.

7 more elements

A memory device, comprising:

a cell array including a first sub cell array and a second sub cell array;
a first bit line sense amplifier connected to the first sub cell array;
a second bit line sense amplifier connected to the second sub cell array;
a first local I/O line pair electrically connected to a first bit line pair connected to the first bit line sense amplifier;
a second local I/O line pair electrically connected to a second bit line pair connected to the second bit line sense amplifier;
a common local I/O line pair, connected to the first local I/O line pair and the second local I/O line pair, the common local I/O line pair including a common local I/O line and a complementary common local I/O line;
a plurality of transmission gate circuits configured to electrically connect the common local I/O line pair to one of the first local I/O line pair or the second local I/O line pair and to electrically isolate the common local I/O line pair from the other of the first local I/O line pair or the second local I/O line pair;
a common local sense amplifier, disposed between a first set of bit line sense amplifiers that includes the first bit line sense amplifier and is connected to the first sub cell array and a second set of bit line sense amplifiers that includes the second bit line sense amplifier and is connected to the second sub cell array, and configured to amplify a voltage level transferred from the common local I/O line pair;
a global I/O line pair connected to the common local sense amplifier;
and
an I/O sense amplifier electrically connected to the global I/O line pair,
wherein the common local sense amplifier comprises:
a first NMOS transistor having a first terminal connected to the common local I/O line and a gate connected to the complementary common local I/O line;
a second NMOS transistor having a first terminal connected to the complementary common local I/O line, a second terminal connected to a second terminal of the first NMOS transistor, and a gate connected to the common local I/O line;
a third NMOS transistor configured to be turned on in response to a first activation signal applied to a gate of the third NMOS transistor, the third NMOS transistor having a first terminal connected to a ground voltage line and a second terminal connected to the second terminals of the first and second NMOS transistors;
a first PMOS transistor having a first terminal connected to the common local I/O line and a gate connected to the complementary common local I/O line;
a second PMOS transistor having a first terminal connected to the complementary common local I/O line, a second terminal connected to a second terminal of the first PMOS transistor, and a gate connected to the common local I/O line;
and
a third PMOS transistor configured to be turned on in response to a second activation signal applied to a gate of the third PMOS transistor, the third PMOS transistor having a first terminal connected to an internal power line and a second terminal connected to the second terminals of the first and second PMOS transistors.

16 more elements

A peripheral circuit, comprising:

a first bit line sense amplifier connected to a first sub cell array of a cell array;
a second bit line sense amplifier connected to a second sub cell array of the cell array;
a first local I/O line pair electrically connected to a first bit line pair connected to the first bit line sense amplifier;
a second local I/O line pair electrically connected to a second bit line pair connected to the second bit line sense amplifier;
a first common local I/O line pair connected to the first local I/O line pair and the second local I/O line pair;
a first common local sense amplifier configured to amplify a voltage level transferred from the first common local I/O line pair;
a global I/O line pair connected to the first common local sense amplifier;
and
an I/O sense amplifier electrically connected to the global I/O line pair,
wherein the peripheral circuit is disposed below or above the cell array.

7 more elements

Dependencies are inferred from the claim text.

Peripheral circuit and memory device including the same

Life of this patent

Peripheral circuit and memory device including the same

Life of this patent

Abstract

Claims20