US 2026/0310744 A1 · IN-MEMORY COMPUTING OF INTERACTIONS BETWEEN VARIABLES OF HIGH-ORDER FUNCTIONS

Abstract

An interaction computation circuit computes interactions between variables (e.g., gradients) of an arbitrary-order function (e.g., polynomial functions or conjunctive normal form (CNF) functions). The circuit includes one or more memory crossbar arrays (“arrays”), each configured to encode the function by associated first wires (e.g., columns) of the array with variables/literals of the function, associating second wires of the array (e.g., rows) with terms of the function, and setting memory cells of the array to an active (conducting) state if the variable/literal corresponding to the first wire coupled to the cell is included in the term corresponding to the second wire coupled to the cell. The circuit computes the interactions in parallel through in-memory computation in the array(s), including conducting a forward pass and one or more backward passes on the array(s). The inputs for the backward pass(es) are determined based on outputs of the forward pass.

Claims24

Dependent claims

An information processing system comprising:

an interaction computation circuit configured to compute interactions between variables of an arbitrary-order function, comprising:
one or more memory crossbar arrays (“arrays”), each configured to encode the function such that:
first wires of the respective array correspond respectively to variables or literals of the function;
second wires of the respective array, transverse to the first wires, correspond respectively to terms of the function;
and
memory cells of the respective array are set to an active state if the variable or the literal corresponding to one of the first wires coupled to the respective memory cell is included in the term corresponding to one of the second wires coupled to the respective memory cell;
and
peripheral circuitry to process inputs to and outputs from the arrays;
wherein the interaction computation circuit is configured to compute the interactions in parallel at least in part by in-memory computation in the arrays, including conducting a forward pass and one or more backward passes on the arrays, with inputs for the backward passes determined by the peripheral circuitry based on outputs of the forward pass.

6 more elements

A hardware accelerator module, comprising:

one or more memory crossbar arrays (“arrays”), each configured to encode an arbitrary-order function such that:
first wires of the respective array correspond respectively to variables or literals of the function;
second wires of the respective array, transverse to the first wires, correspond respectively to terms of the function;
and
memory cells of the respective array are set to an active state if the variable or the literal corresponding to one of the first wires coupled to the respective memory cell is included in the term corresponding to one of the second wires coupled to the respective memory cell;
and
peripheral circuitry configured to compute the gradient by:
conducting a forward pass by applying signals corresponding to an input variable vector or a complement thereof to the first wires of a first array of the arrays and observing forward pass outputs from the second wires of the first array;
conducting a backward pass by applying signals to the second wires of a second array of the arrays based on the forward pass outputs and observing backward pass outputs from the first wires of the second array;
and
computing the gradient based on the backward pass outputs.

8 more elements

Dependencies are inferred from the claim text.

In-memory computing of interactions between variables of high-order functions

Life of this patent

In-memory computing of interactions between variables of high-order functions

Life of this patent

Abstract

Claims24