Multiple instruction multiple data processing unit

A processing method comprising:

• receiving, by each subset of a plurality of modules comprised in a processing unit, a respective total number of inputs, wherein the processing unit comprises a plurality of modules divided into N subsets of modules, wherein the subsets of modules are connected in series from a first subset to an Nth subset, wherein each module receives a first number of inputs and to compute an output, and wherein the first number of inputs is equal to 2;
• and
• processing, by each subset of modules comprised in the processing unit, the respective total number of inputs received by each subset, wherein each module of the subset of modules processes the first number of inputs from the respective total number of inputs received by the subset of modules to compute the output of the module in parallel with the other modules of the subset of modules during one clock cycle, and wherein the output of the module is transferred, in parallel with the other modules of the subset of modules, as an input to the respective subsequent subset of modules connected in series,
• wherein processing, by each subset of modules comprised in the processing unit, the respective total number of inputs received by each subset comprises transferring, simultaneously with the other modules of the subset of modules, a start bit, to a corresponding module of the respective subsequent subset of modules, wherein the start bits are simultaneously transferred to the corresponding modules in a first time interval preceding a second time interval, wherein the second time interval is the time interval in which the least significant bits, LSBs, of the respective total number of inputs are simultaneously transferred to the corresponding modules of the respective subsequent subset of modules, and wherein a time interval comprises one or more clock cycles.