Scalable interconnection-network-centric memory expansion systems for accelerators

A method of controlling a plurality of tiers of compute nodes and a plurality of tiers of memory nodes coupled to the corresponding tiers of compute nodes,

• the plurality of tiers of compute nodes including a first tier of compute nodes comprising one or more Graphics Processing Units (GPUs) and a second tier of compute nodes comprising one or more Central Processing Units (CPUs),
• the plurality of memory nodes including a first tier of memory nodes and a second tier of memory nodes having lower bandwidth than the first tier of memory nodes,
• the method comprising:
• sharing, by the plurality of tiers of compute nodes, the plurality of memory nodes using an interconnection network;
• and
• storing, by one or more controllers, data in one of the first tier of memory nodes or the second tier of memory nodes, based on one or more characteristics of the data.

Circuitry for controlling a plurality of tiers of compute nodes and a plurality of tiers of memory nodes coupled to the corresponding tiers of compute nodes,

• the plurality of tiers of compute nodes including a first tier of compute nodes comprising one or more Graphics Processing Units (GPUs) and a second tier of compute nodes comprising one or more Central Processing Units (CPUs),
• the plurality of memory nodes including a first tier of memory nodes and a second tier of memory nodes having lower bandwidth than the first tier of memory nodes,
• the circuitry comprising one or more controllers configured to:
• control the plurality of tiers of compute nodes to share the plurality of memory nodes using an interconnection network;
• and
• store data in one of the first tier of memory nodes or the second tier of memory nodes, based on one or more characteristics of the data.