Hardware Mechanism for Universal Synchronization of Communications in an SOC

A system comprising:

• a hardware sync unit, a processing device, and a non-transitory machine-readable storage device storing instructions that are executable by the processing device to cause performance of operations comprising:
• generating, by the hardware sync unit, a global sync object that is used to control and manage one or more synchronization events at the SoC;
• determining, by the hardware sync unit, a plurality of context states with reference to the global sync object, each of the plurality of context states corresponding to a respective IP device of a plurality of IP devices on the SoC;
• generating, at the hardware sync unit, a plurality of register values that represent each of the plurality of context states corresponding to each respective IP device;
• and
• managing, by the hardware sync unit, an execution of synchronization events involving each of the plurality of IP devices based on the global sync object and the plurality of register values.

A non-transitory machine-readable storage device storing instructions that are executable by a processing device to cause performance of operations involving a hardware sync unit, the operations comprising:

• generating, by the hardware sync unit, a global sync object that is used to control and manage one or more synchronization events at the SoC;
• determining, by the hardware sync unit, a plurality of context states with reference to the global sync object, each of the plurality of context states corresponding to a respective IP device of a plurality of IP devices on the SoC;
• generating, at the hardware sync unit, a plurality of register values that represent each of the plurality of context states corresponding to each respective IP device;
• and
• managing, by the hardware sync unit, an execution of synchronization events involving each of the plurality of IP devices based on the global sync object and the plurality of register values.