Metal frame chip embedded packaging substrate and manufacturing method thereof

A method for manufacturing a metal frame chip embedded packaging substrate, the method comprising:

• preparing a metal plate;
• forming a cavity penetrating the metal plate and a metal frame surrounding the cavity on the metal plate, and selectively partially etching a first surface of the metal frame to form a first groove on the metal frame;
• embedding a chip in the cavity so that a patterned side of the chip faces the first surface, and laminating a dielectric layer on a second surface of the metal frame opposite the first surface, wherein the dielectric layer covers a back side of the chip and fills the first groove;
• forming a blind hole and a window on the dielectric layer, the blind hole being configured to expose the second surface of the metal frame, and the window being configured to expose the back side of the chip;
• and
• forming a first wiring layer on the first surface and a second wiring layer on the second surface,
• wherein the second wiring layer is connected to the back side of the chip through a first conducting post formed by electroplating the window, and is connected to the metal frame through a second conducting post formed by electroplating the blind hole, wherein the first wiring layer is connected to a terminal of the chip.