Embedded ferroelectric capacitors in the back end of line for ferroelectric random access memory

An apparatus, comprising:

• a stack structure including a plurality of layers, wherein a first layer of the plurality of layers includes a first interconnect structure and a first dielectric material;
• and
• a ferroelectric capacitor in a cavity within the stack structure, wherein the ferroelectric capacitor is conductively coupled to the first interconnect structure in the first layer and is further conductively coupled to a first transistor in a device layer, wherein one or more of the plurality of layers of the stack structure are disposed between the device layer and the ferroelectric capacitor.

An apparatus, comprising:

• a plurality of interconnect layers including at least one dielectric material, a first interconnect layer comprising a first interconnect structure, and a second interconnect layer above the first interconnect layer;
• and
• a capacitor embedded in at least the second interconnect layer of the plurality of interconnect layers, wherein the capacitor includes an inner conductive portion, an outer conductive portion, and a dielectric portion comprising ferroelectric material and located between the inner conductive portion and the outer conductive portion, wherein the first interconnect structure couples the outer conductive portion of the capacitor to a first transistor below the first interconnect layer.